A NOR array architecture allowing single bit, row, and column programming and row erase operations, said NOR array architecture comprising:
- a plurality of ETOX cells formed in a p-well, each of said ETOX cell having:
- (1) a control gate;
- (2) a floating gate insulated from and formed underneath said control gate;
- (3) an n-type drain formed in said p-well adjacent to said floating gate;
- and
- (4) a p-type source formed in said p-well adjacent to said floating gate;
- wherein said ETOX cells are formed into a two-dimensional array including a plurality of rows and a plurality of columns;
- further wherein each of said control gates of said ETOX cells sharing a common row are connected to a row wordline;
- further wherein each of said n-type drain of said ETOX cells sharing a common column are connected to a column bitline;
- and
- further wherein each of said p-type source of said ETOX cells is connected to said p-well.