Method for manufacturing split-gate flash memory cell

A method for manufacturing a split-gate flash memory cell comprising the steps of:

• providing a semiconductor substrate having at least one multi-layer gate structure formed thereon, wherein the multi-layer gate structure includes a first conductive layer, a dielectric layer, a second conductive layer and a silicon nitride layer;
• forming a first spacer around the sides of the multi-layer gate structure;
• forming a first polysilicon layer over the multi-layer gate structure and above the semiconductor substrate;
• forming an oxide layer over the first polysilicon layer;
• etching back to remove a portion of the oxide layer and forming a second spacer around the sides of the first polysilicon layer;
• using the second spacer as a mask, performing a first ion implantation implanting ions into the semiconductor substrate to form a drain region;
• removing the second spacer;
• forming a photoresist layer over the first polysilicon layer;
• forming a mask to expose an area for forming the source region;
• implanting ions into the exposed area to form a source region in the semiconductor substrate;
• removing the photoresist layer;
• forming a second polysilicon layer over the first polysilicon layer;
• and
• forming a tungsten silicide layer over the second polysilicon layer.