Method for manufacturing memory cell with trench capacitor
AssigneeInfineon Technologies North America Corp.
InventorsByeong Y. Kim, Carl Radens, Jochen Beintner
Life of this patent
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Abstract
A memory cell includes a transistor and a capacitor that is a doped polysilicon filled trench. A doped polycrystalline strap provides a low resistance connection between a source region of the transistor and the polysilicon fill and is shaped to overlie both a top surface and a side surface of the source region of the transistor.
Claims6
A method of forming in a silicon chip a memory cell that includes as a capacitor a polysilicon filled trench and a field effect transistor that includes a source region comprising the steps of:
- forming over a top surface of the chip a masking layer that has an opening of a first area;
- forming adjacent the source region of the transistor a trench with vertical side walls and a cross section matching that of the opening in the masking layer;
- forming a dielectric layer over the surface of the trench for use as the capacitor dielectric;
- partially filling the trench with doped polysilicon, leaving a top portion unfilled;
- enlarging the area of the opening in the masking layer for exposing a portion of the top surface of the silicon chip surrounding the trench;
- forming a dielectric collar over the exposed trench-surrounding portion of the top surface of the chip and the surface of the unfilled top portion of the trench;
- removing the dielectric collar selectively from a portion of the top surface of the chip surrounding the trench and both the dielectric collar and the dielectric layer from a top portion of the sidewall of the trench;
- depositing conductive polysilicon both in the unfilled top portion of the trench and over the exposed top surface of the chip surrounding the trench for providing a low resistance connection between the source region in the chip and the polysilicon fill in the trench;
- and
- removing any deposited polysilicon that makes unwanted low resistance connection to other portions of the chip.
A method for the manufacture of a dynamic random access memory comprising the steps of:
- forming at the top surface in a silicon layer first and second spaced regions of one conductivity type and intermediate therebetween a region of the opposite conductive type;
- forming a dielectric layer for use as a mask on said top surface;
- forming an opening in the dielectric mask for defining the location of a vertical trench in the wafer to be adjacent to said second spaced region of one conductivity type;
- forming a vertical trench in the silicon wafer defined by said opening and adjacent to the second spaced region;
- forming a dielectric layer on the wall of said trench for serving as the dielectric of a capacitor;
- partially filling the trench with doped polysilicon, and leaving exposed silicon at the side wall of the unfilled portion;
- enlarging the opening in the dielectric mask on the top surface of the wafer for exposing a surface portion surrounding the trench;
- forming a dielectric collar on the exposed side wall of said partially filled trench and on the exposed surface portion surrounding the trench;
- etching the dielectric collar to expose selectively portions of the top and side surfaces of said second spaced region;
- depositing doped polysilicon over the top surface of the layer to contact the exposed top and side surface of said second spaced region and to form a conductive connection between the fill in the trench and the second spaced region;
- and
- forming a shallow trench of oxide in the silicon layer for isolating the cell from adjacent cells in the layer.
Dependencies are inferred from the claim text.