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US 6,143,594 AGranted
On-chip ESD protection in dual voltage CMOS
AssigneeTexas Instruments Incorporated
InventorsAlwin J. Tsao, Vikas I. Gupta, Gregory C. Baldwin, E. Ajith Amerasekera, David B. Spratt, Timothy A. Rost
Life of this patent
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Abstract
In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.
Claims5
A fabrication method for an integrated circuit, comprising the steps of:
- (a.) fabricating a first plurality of NMOS transistors with a first gate oxide thickness, a first channel doping profile, and a first drain extender doping profile;
- (b.) fabricating a second plurality of NMOS transistors with a second gate oxide thickness, a second channel doping profile, and a second drain extender doping profile;
- (c.) fabricating a third plurality of NMOS transistors with said second gate oxide thickness, said first channel doping profile and said first drain extender doping profile.
Dependencies are inferred from the claim text.