Field isolated integrated injection logic gate

A semiconductor device which comprises:

• a substrate of a first conductivity type;
• a buried layer of a second type conductivity type adjacent said substrate;
• buried regions of a first conductivity type adjacent said buried layer of second type conductivity;
• a deeply buried region of a second conductivity type adjoining said buried layers of second type conductivity on each side thereof and forming a ring of said second conductivity type;
• epitaxially grown silicon regions of a second conductivity;
• an implanted region of the first conductivity type underlying at least a portion of a lateral PNP, a metal base contact, n+ polysilicon collectors, and field oxide isolation regions or shallow trench isolation regions;
• regions of the first conductivity type overlying portions of said n-epitaxial region, portions of said epitaxial region underlying said p+ regions and being of the first conductivity type;
• field oxide regions or shallow trench isolation regions adjacent said ring of second conductivity type and said epitaxial regions of a second conductivity type, respectively;
• silicide layers overlying said regions of first conductivity type;
• said lateral PNP transistor being formed by said regions of first conductivity type and said epitaxial region of second conductivity type;
• a metal base contact overlying said region of first conductivity type and said silicide layer;
• an I2L device having multiple collectors of an upside down NPN transistor adjacent multiple regions of the second conductivity type caused by n+ outdiffusion of n+ polysilicon into said epitaxial regions, isolated between said field oxide regions or shallow isolation trench regions,
• wherein each collector of the I2L device is isolated by one of said field oxides or shallow isolation trenches, and the connection of the base to the collectors, between the base contact region and the bottom of the collectors, is made underneath the field oxide or shallow isolation trench using the buried layer of first conductivity type.

A semiconductor device which comprises:

• a substrate of a p-type silicon substrate;
• a buried layer of n-type conductivity adjacent the substrate;
• buried regions of a p-conductivity type adjacent said buried layer of n-type conductivity;
• a deeply buried region of a n-conductivity type adjoining said buried layers of n-type conductivity on each side thereof and forming a DN ring of said n-type conductivity;
• epitaxially grown silicon regions of the n-type conductivity;
• a TN3 implanted region of the p-type conductivity underlying at least a portion of a lateral PNP, a metal base contact, n+ polysilicon collectors, and field oxide isolation regions or shallow trench isolation regions;
• p+ regions overlying portions of said n-epitaxial region, portions of said n-epitaxial region underlying the p+ regions and being of the first conductivity type;
• field oxide regions or shallow trench isolation regions adjacent said DN ring and said n-epitaxial regions, respectively;
• silicide layers overlying said p+ regions;
• said lateral PNP transistor being formed by said p+ regions and said n-epitaxial region;
• a metal base contact overlying said silicide layer and said p+ region;
• an I2L device having multiple collectors of an upside down NPN transistor adjacent multiple n-type regions caused by n+ outdiffusion of n+ polysilicon into said n-epitaxial regions isolated between said field oxide regions or shallow isolation trench regions, wherein each collector of the I2L device is isolated by one of said field oxides or shallow isolation trenches, and the connection of the base to the collectors, between the base contact region and the bottom of the collectors, is made underneath the field oxide or shallow isolation trench using the TN3 buried layer of p-type conductivity.