US 6,137,152 AGranted

Planarized deep-shallow trench isolation for CMOS/bipolar devices

AssigneeTexas Instruments - Acer Incorporated

InventorShye-Lin Wu

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Abstract

The trench isolation structure in the present invention is as follows. A lower-half trench is in the substrate. An upper-half trench in the substrate is located above the lower-half trench and the upper-half trench has a larger width than the lower-half trench. A first insulating layer is right above the lower-half trench and the upper-half trench. A second insulating layer is located over the first insulating layer. A semiconductor layer is within the lower-half trench over a portion of the second insulating layer. A third insulating layer is located on the second insulating layer and the semiconductor layer and is located within the upper-half trench. The planarized deep-shallow trench isolation in the present invention can be employed for isolating CMOS and bipolar devices. A higher packing density than conventional trench isolation is provided.

Claims3

Dependent claims

A trench isolation before planarization formed on a substrate, said trench isolation comprising:

a nitride layer formed on said substrate;
a first trench with a first opening having a first width formed in said substrate and said nitride layer;
a second trench with a second opening having a second width formed in the bottom of said first trench and extending into said substrate, wherein said second width is narrower than said first width, a depth of said second trench is deeper than that of said first trench;
a first oxide layer for relieving a stress lying on the surface of said second trench, on the lower part of said first trench and between the interface of said substrate and said nitride layer;
an oxynitride layer acting as an oxidation buffer to improve the isolation formed along the upper surface of said nitride layer, the surface of said first trench and along the surface of said first oxide layer formed on the surface of said second trench;
a polysilicon plug refilled in said second trench;
a second oxide layer refilled into said first trench and on the upper surface of said oxynitride layer that lying on said nitride layer;
and
a filling layer formed on said second oxide layer for said planarization.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/064,976Filed 22 Apr 1998
Granted: 24 Oct 2000
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H10W 10/17
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
H10W 10/0142
Using trench refilling with dielectric materials, e.g. shallow trench isolations: the dielectric materials being chemical transformed from…
H10W 10/0145
Using trench refilling with dielectric materials, e.g. shallow trench isolations: of trenches having shapes other than rectangular or V-shape
H10W
Generic packages, interconnections, connectors or other constructional details of devices covered by