Variable delay element

A memory control system comprising:

• a master device;
• a plurality of memory units coupled to the master device via a channel, wherein at least one of the plurality of memory units includes a memory interface, the memory interface comprising:
• a transceiver circuitry adapted to receive control signals from the master device;
• a decoder circuit adapted to translate the control signals;
• and
• a phase interpolator coupled to the decoder circuit, the phase interpolator comprising:
• a phase interpolator circuit having a voltage input terminal and a voltage output terminal;
• and
• a controllable capacitive load coupled to the voltage input terminal of the phase interpolator circuit for providing a controllable amount of capacitance at the output terminal to improve linearity of the phase interpolator, whereby a variable capacitance is presented at the voltage input terminal in response to control of the capacitive load.

An adjustable phase interpolator comprising:

• a phase interpolator circuit having at least one voltage input and a voltage output providing an output signal having a predetermined voltage swing;
• a controllable resistive load coupled to the voltage output of the phase interpolator circuit, wherein the controllable resistive load is adjusted to improve linearity of the phase interpolator;
• and
• a controllable current source coupled to the controllable resistive load for varying in inverse relation to the controllable resistive load, such that the voltage swing of the output signal is maintained when the controllable resistive load is adjusted.

The adjustable phase interpolator of claim 17, wherein the phase interpolator circuit comprises:

• a first transistor pair including a first transistor and a second transistor having sources commonly coupled;
• a second transistor pair including a third transistor and a fourth transistor having sources commonly coupled;
• first and second controllable tail current sources, the first controllable tail current source being coupled to the commonly coupled sources of the first and second transistors, and the second controllable tail current source being coupled to the commonly coupled sources of the third and fourth transistors;
• wherein the controllable resistive load, further comprises:
• a first variable resistive load commonly connected to the drains of the first and third transistors, and
• a second variable resistive load commonly connected to the drains of the second and fourth transistors.

A phase interpolator responsive over a predetermined range of frequencies, comprising:

• a phase interpolator having at least one input and an output;
• a current source coupled to the phase interpolator;
• a variable resistive load coupled to the output of the phase interpolator;
• a variable capacitive load coupled to at least one of the at least one input and output of the phase interpolator for providing a controllable amount of capacitance at the output to improve linearity of the phase interpolator;
• wherein adjustment of at least one of the variable resistive load, or and the variable capacitive load causes the phase interpolator to adjust operating frequency within the predetermined range of frequencies.

An adjustable phase interpolator comprising:

• a phase interpolator circuit comprising a first input receiving a first signal with a first phase, and a second input receiving a second input signal with a second phase, wherein the first and second input signals have substantially the same frequency;
• the phase interpolator circuit further comprising an output producing an output signal with a phase between the first phase and the second phase;
• and
• a variable capacitive load coupled to the output of the phase interpolator circuit and receiving a control signal for providing a controllable amount of capacitance at the output of the phase interpolator to improve linearity of the phase interpolator, wherein the capacitance apparent at the output of the phase interpolator circuit and operating frequency of the phase interpolator circuit are adjusted in accordance with the control signal.

An adjustable phase interpolator comprising:

• a phase interpolator circuit comprising a first input receiving a first input signal with a first phase, and a second input receiving a second input signal with a second phase, the first and second input signals having the same frequency;
• the phase interpolator circuit further comprising an output producing an output signal having a phase within a predetermined range bounded by the first phase and the second phase;
• and
• a first variable capacitive load coupled to the first input of the phase interpolator circuit for providing a controllable amount of capacitance at the output of the phase interpolator to improve linearity of the phase interpolator, wherein the first variable capacitance load receives a first control signal adjusting the capacitance of the first variable capacitive load such that a first operating frequency of the phase interpolator circuit is determined within the predetermined range.

An adjustable phase interpolator comprising:

• a phase interpolator circuit comprising a first input receiving a first input signal with a first phase and a second input receiving a second input signal with a second phase, the first input and the second input signals having the same frequency;
• the phase interpolator circuit further comprising an output node producing an output signal having an output phase within a predetermined range bounded by the first phase and the second phase;
• and
• a controllable resistive load circuit coupled to the output node and receiving a resistance control signal for adjusting resistance of the controllable resistive load circuit to improve linearity of the phase interpolator;
• wherein the controllable resistive load circuit is adjusted to provide the operating frequency for the phase interpolator circuit within the predetermined range.