Scaleable padframe interface circuit for FPGA yielding improved routability and faster chip layout

An interface circuit for coupling input and output signal lines from buses that run through an array of logic circuits in field programmable gate array integrated circuit, comprising:

• a plurality of input/output cells each of which can be programmed to be either a data input port for receiving input signals from an external source onto one or more input signal lines of said buses, or a data output port for outputting data output signals received from one or more of said output signal lines of said buses to external pins or output conductors of said integrated circuit available to the outside world, or both a data output and a data input for receiving a data output signal on a first conductor from said buses and driving the signal onto a second conductor from said buses which is different from said first conductor;
• a plurality of buses each comprised of a plurality of individual data input conductors for carrying data input signals from external sources to an array of logic blocks of an integrated circuit and data output signal conductors for carrying data output signals generated by logic circuits in said array of logic blocks to pins or output conductors available to the outside world;
• and
• a programmable connection matrix providing programmable connections between said data input conductors and said data output conductors of said plurality of buses and said input/output cells, and wherein said programmable connection matrix implements every programmable connection using an active repeater where an active repeater is defined as a transistor switching circuit and output stage coupled to high and low voltage conductors of an external power supply when in operation which functions, when enabled, to programmably couple the digital signal propagating on a first conductor to a second conductor by using transistor action under the influence of the input signal propagating in said first conductor to selectively couple said high voltage conductor of said external power supply to said second line segment to charge the parasitic capacitance loading said second conductor or couple the low voltage conductor of said external power supply to discharge the parasitic capacitance loading said second conductor in accordance with the logic transitions of said input signal.

An interface circuit for interfacing logic blocks in a core array of programmable logic blocks of an integrated circuit to a plurality of external pins of an integrated circuit, said interface circuit having an integrated circuit layout comprising:

• a fixed number of input/output cells each of which may be programmed as either an input or an output, or both, and each of which is electrically coupled to an external pin of an integrated circuit, each said I/O circuit including programming circuitry controlling whether said I/O circuit operates as an input, an output or both;
• a fixed number of I/O power and ground ports connected to external pins of an integrated circuit and connected to said input/output cells to supply power thereto, said fixed number of I/O power and ground ports established at a number which is high enough to supply adequate current considering the number of input/output cells in said interface circuit;
• at least one empty slot for use in laying out power or ground connections from at least one external pin of said integrated circuit to said core array or for making connections from at least one external pin to other circuitry not part of said core array to carry one or more signals needed by said other circuitry;
• a plurality of buses each comprising a plurality of data output signal lines carrying data output signals from said core array and a plurality of data input signal lines carrying data input signals to said core array;
• and
• a programmable connection matrix coupling said input/output cells to said plurality of data output signal lines and said data input signal lines via a plurality of programmable signal pathways via programmable connections made using an active repeater at every or substantially every programmable connection point.

A process for laying out an integrated circuit for a field programmable gate array comprising cutting and pasting a sufficient number of predesigned, substantially identical interface circuits to make connections between a plurality of data input and data output signals lines of buses running through a core array of programmable logic blocks in said field programmable gate array and the external pins of the integrated circuit, each of said substantially identical interface circuits having a plurality of programmable input/output cells for coupling to external pins which can be programmed as either data inputs or data outputs or both in the sense that data signals entering the input/output cell from a data output signal line of a bus may be turned around in an input/output cell and coupled back into said array of logic blocks as a data input signal, each of said substantially identical interface circuits having a plurality of power and ground connections from external pins to the input/output cells which are adequate to supply enough power to that number of input/output cells, and having at least one empty slot and having a programmable connection matrix through which pathways may be programmed via active repeaters to make connections between said input/output cells and the data input and data output signal lines in a core array of programmable logic blocks of said field programmable gate array, wherein each said active repeater in said predesigned, substantially identical interface circuits is implemented with one or more switching transistors which are coupled to an external power supply when operational and programmed to regenerate on an output conductor an input signal appearing at an input of said active repeater by using the large current drive and current sink capacity of the external power supply to selectively charge or discharge parasitic capacitance loading said output of said active repeater in accordance with the logic transitions of the input signal so as to speed up the rise and fall times of the logic transitions created on said output conductor relative to corresponding logic transitions of the input signal.

A collection of interface circuits for use as a padframe interface between the core array of logic blocks of a field programmable gate array integrated circuit and at least some of the external pins of the integrated circuit, each said interface circuit having any interface circuit structure suitable to perform the interface task defined above and characterized by the following features:

• each interface circuit has the same structure and includes the same number of input/output cells each of which may be programmed as a data input or a data output or both, the same number of I/O power and ground connections and the same number of open spaces;
• each interface circuit includes a programmable connection matrix which provides programmable data pathways between said input/output cells and data input and data output signal lines coming from said core array via programmable connections made through use of an active at every or substantially every programmable connection point;
• each interface circuit includes enough power and ground pathways between external pins and said input/output cells to supply sufficient current to operate said input/output cells;
• each interface circuit includes at least one open space in which a conductive pathway may be laid out on the integrated circuit to carry dedicated signals to circuits other than said core array which need said signals or which carry current to said core array;
• and wherein larger or smaller size core arrays have their padframe interface circuits characterized by more of said interface circuits placed in the padframe interface circuit integrated circuit layout such that the ratio of input/output cells to I/O power and ground connections to open spaces remains unchanged.

A repeatable interface unit circuit for use in the padframe interface circuit area of a field programmable gate array integrated circuit comprising:

• input/output cell means for providing a plurality of programmable data pathways to external pins of an integrated circuit, some of said pathways being programmable as data inputs and some of said pathways being programmable as data outputs, and some of said input/output cells programmable to be both inputs and outputs;
• a plurality of data buses each of which includes a plurality of data output conductors for carrying data output signals from an array of logic blocks of the core array of said field programmable gate array and each of which includes a plurality of data input conductors for carrying data input signals to said array of logic blocks from said external pins;
• and
• programmable connection matrix means including a plurality of active repeaters at every or substantially every programmable connection point for allowing a plurality of programmable data pathways to be established between selected ones of said data output conductors of said buses and data output pathways of said input/output cell means, and for allowing a plurality of programmable data pathways to be established between selected ones of said data input conductors of said buses and data input pathways of said input/output cell means.

A repeatable interface unit circuit for use in the padframe interface circuit area of a field programmable gate array integrated circuit comprising:

• input/output cell means for providing a plurality of programmable data pathways to external pins of an integrated circuit, some of said pathways being programmable as data inputs and some of said pathways being programmable as data outputs, and some of said input/output cells programmable to be both inputs and outputs:
• a plurality of data buses each of which includes a plurality of data output conductors for carrying data output signals from an array of logic blocks of the core array of said field programmable gate array and each of which includes a plurality of data input conductors for carrying data input signals to said array of logic blocks from said external pins;
• and
• programmable connection matrix for allowing a plurality of programmable data pathways to be established between selected ones of said data output conductors of said buses and data output pathways of said input/output cell means, and for allowing a plurality of programmable data pathways to be established between selected ones of said data input conductors of said buses and data input pathways of said input/output cell means;
• and wherein said input/output cell means provides eight programmable pathways which may be programmed as data inputs or data outputs, and wherein said interface circuit couples to four columns each of which has twenty-four data output conductors and six data input conductors, and wherein said programmable connection matrix allows programmable data pathways to be established between as many as eight of said programmable pathways programmed as data inputs and up to a three simultaneously of the six data input conductors of each of the four columns, provided no two or more programmable pathways programmed as data inputs are simultaneously connected to drive the same data input conductor of a column with two or more different data input signals.

A repeatable interface unit circuit for use in the padframe interface circuit area of a field programmable gate array integrated circuit comprising:

• input/output cell means for providing a plurality of programmable data pathways to external pins of an integrated circuit, some of said pathways being programmable as data inputs and some of said pathways being programmable as data outputs, and some of said input/output cells programmable to be both inputs and outputs;
• a plurality of data buses each of which includes a plurality of data output conductors for carrying data output signals from an array of logic blocks of the core array of said field programmable gate array and each of which includes a plurality of data input conductors for carrying data input signals to said array of logic blocks from said external pins;
• and
• programmable connection matrix for allowing a plurality of programmable data pathways to be established between selected ones of said data output conductors of said buses and data output pathways of said input/output cell means, and for allowing a plurality of programmable data pathways to be established between selected ones of said data input conductors of said buses and data input pathways of said input/output cell means;
• and wherein said programmable connection matrix further comprises a plurality of I.sub.-- lines which can be programmably coupled to each of the eight programmable pathways which can be programmed as inputs, and wherein said programmable connection matrix of each RIU interface circuit further comprises a first and second plurality of O.sub.-- lines, each of which may be programmably connected to first and second halves of said programmable pathways of said input/output cell means, respectively, and each of which may be programmably connected to first and second pairs of said four columns, respectively, such that any of said first or second half of programmable pathways which are programmed as data outputs can be connected in programmable fashion to any of up to fourteen selected ones of the twenty-four data output conductors of either of the two columns in the pair of columns to which said first or second half of programmable pathways are coupled through said first or second plurality of O.sub.-- lines, respectively, provided that no programmable data pathway programmed as a data output can be simultaneously driven by more than one data output signal from any one or more columns, and provided that no O.sub.-- line can be simultaneously driven by more than one data output signal from any one or more columns, and wherein said first and second plurality of O.sub.-- lines within each RIU interface circuit have individual O.sub.-- lines each of which is divided into two line segments joined by an active repeater, and wherein said I.sub.-- lines of each said RIU interface circuit are joined on both ends by active repeaters to the I.sub.-- lines of neighboring RIU interface circuits.

A repeatable interface circuit for an integrated field programmable gate array having a core array of programmable logic circuits comprising:

• first and second pluralities of programmable I/O cells any one of which can be programmed to act as a data input or data output port for an integrated circuit, each I/O cell having a Do input for receiving a data output signal, an OE output enable input for receiving a signal which enables said I/O cell to drive any signal received at said Do input to an external pin and a CKE clock enable input for receiving a clock enable signal, and having a Din output at which a data input signal is presented if said I/O cell is programmed as a data input and having at least one programming signal input;
• means coupled to the at least one programming signal input of said first and second pluralities of programmable I/O cells for supplying one or more programming signals that define whether each said I/O cell acts as a data input or a data output or both;
• a first plurality of intermediary O.sub.-- line conductors;
• a second plurality of intermediary O.sub.-- line conductors, each said intermediary O.sub.-- line conductor terminating on one end at the input of a tri-state driver type active repeater which has an output which is coupled to one of the intermediary O.sub.-- line conductors of said first plurality of intermediarly O.sub.-- line conductors, and terminating at the other end at the input of a tri-state driver type active repeater having an output for coupling to an intermediary O.sub.-- line conductor of an adjacent repeatable interface circuit;
• a plurality of intermediary I.sub.-- line conductors each said intermediary I.sub.-- line conductor terminating on both ends at the input of a tri-state driver type active repeater which has an output for coupling to an intermediary I.sub.-- line conductor of an adjacent repeatable interface circuit;
• first, second and third active repeater type multiplexers associated with each I/O cell in said first plurality of I/O cells and having first, second and third outputs coupled to said Do, OE and CKE inputs, respectively, of the associated I/O cell, and having a plurality of inputs each of which is connected to a selected one or more of said first plurality of O.sub.-- line conductors, said first, second and third multiplexers associated with each I/O cell in said first plurality of I/O cells having select inputs for receiving signals which control which input of each multiplexer is coupled to its output, and wherein each active repeater type multiplexer is implemented with switching transistors which are coupled to an external power supply when operational and programmed to select an input for coupling to said output of said multiplexer so as to use the large current drive and current sink capacity of the external power supply to charge or discharge parasitic capacitance loading said output of said multiplexer in accordance with the logic transitions of the input signal of the selected input to be coupled to said output;
• fourth, fifth and sixth active repeater type multiplexers associated with each I/O cell in said second plurality of I/O cells and having first, second and third outputs coupled to said Do, OE and CKE inputs, respectively, of the associated I/O cell, and having a plurality of inputs each of which is connected to a selected one or more of said second plurality of O.sub.-- line conductors, said fourth, fifth and sixth multiplexers associated with each I/O cell in said second plurality of I/O cells having select inputs for receiving signals which control which input of each multiplexer is coupled to its output, said fourth, fifth and sixth active repeaters having the same structure as said first, second and third multiplexers;
• means coupled to said select inputs of said first, second, third, fourth, fifth and sixth multiplexers for providing programmable signals to said select inputs to control which input of each multiplexer is coupled to that multiplexer's output;
• a first plurality of active repeaters in the form of tri-state drivers programmably coupling said Din output of each I/O cell to a selected one or more of said plurality of intermediary I.sub.-- lines;
• a plurality of output lines from each of a plurality of buses comprised of conductors that pass through said array of programmable logic circuits carrying output signals therefrom;
• a plurality of input lines in each of said plurality of buses for carrying input signals to said array of logic circuits
• a second plurality of active repeaters in the form of tri-state drivers programmably coupling said plurality of output lines from said buses to selected ones of said first and second pluralities of intermediary O.sub.-- lines;
• and
• a third plurality of active repeaters in the form of tri-state drivers programmably coupling said plurality of input lines in said buses to selected ones of said plurality of intermediary I.sub.-- lines;
• and wherein each said active repeater is implemented with one or more switching transistors which are coupled to an external power supply when operational and programmed to be in an enabled state so as to regenerate on an output conductor an input signal appearing at an input of said active repeater by using the large current drive and current sink capacity of the external power supply to selectively charge or discharge parasitic capacitance loading said output of said active repeater in accordance with the logic transitions of the input signal so as to speed up the rise and fall times of the logic transitions created on said output conductor relative to corresponding logic transitions of the input signal, and wherein each active repeater includes programming means for controlling whether said active repeater is enabled or disabled.