High density planar SRAM cell with merged transistors
AssigneeMicron Technology, Inc.
InventorsWendell P. Noble, Jr., Leonard Forbes
Life of this patent
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Abstract
Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes gates which are pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.
Claims51
A memory cell, comprising a gated diode having bistable current states for storing information, one of said current states being achieved by operation of gate-induced latch-up of said diode, said gated diode comprising a p-n-p-n four-region diode
- wherein said memory cell is linked to a second memory cell having a gated p-n-p-n diode so that the two p-n-p-n diodes share a common n-region.
A circuit for storing information as one of at least two possible stable current states, comprising:
- a multi-region thyristor having at least four regions;
- and
- at least two gates in contact with a junction of said multi-region thyristor, wherein said gates are connected to a voltage source for producing latch-up in said multi-region thyristor.
An SRAM array, comprising:
- at least one memory cell having a four-region latch with a first gate in contact with a first and a second junction of said four-region latch, and with a second gate in contact with the second and a third junction of said four-region latch, wherein said gates are connected to a voltage source for producing latch-up in said four-region latch.
An SRAM array, comprising:
- a substrate;
- a plurality of planar four-region transistors each having two gates;
- and
- gate lines connecting the gates to a voltage source for producing latch-up in said four-region transistors.
A processor based system, comprising
- a processor;
- and
- a memory circuit connected to the processor, the memory circuit containing at least one memory cell comprising a gated four region diode having bistable current states for storing information, one of said current states being achieved by operation of gate-induced latch-up of said four diode region, said at least one memory cell being linked to another memory cell comprising a gated four-region diode so that the two-four-region diodes share a common region.
A method of forming a circuit for storing information as one of at least two possible stable current states, the method comprising the following steps:
- providing a semiconductor substrate;
- providing doped silicon regions to form a multi-region planar thyristor having at least four regions;
- forming at least two polysilicon gates in connection with at least two separate junctions of said multi-region planar thyristor;
- and
- connecting said at least two polysilicon gates to a voltage source for producing latch-up in said multi-region planar thyristor.
Dependencies are inferred from the claim text.