High-speed comparator with improved latch accuracy

A comparator having an input signal port and an output signal port and responsive to an input signal at said input signal port and to a latch signal, comprising:

• a differential input amplifier which includes an input differential pair of transistors having first and second control structures that form said input signal port;
• a differential output amplifier that forms said output signal port and is responsive to said input differential pair of transistors;
• a clamp that is coupled between said first and second control structures to limit the amplitude of said input signal between said input differential pair of transistors;
• and
• a latch which receives said latch signal and, in response, maintains a current state of said differential output amplifier;
• and further including a bias structure that generates first and second bias signals and wherein said clamp includes first and second diodes that are oppositely oriented and that are coupled to said first control structure and also coupled to receive said first and second bias signals.

A comparator having an input signal port and an output signal port and responsive to an input signal at said input signal port and to a latch signal, comprising:

• a differential input amplifier which includes an input differential pair of transistors having first and second control structures that form an input port;
• a differential output amplifier that forms an output port and is responsive to said input differential pair of transistors;
• a clamp that is coupled between said first and second control structures to limit the amplitude of said input signal between said input differential pair of transistors;
• and
• a latch which receives said latch signal and, in response, maintains a current state of said differential output amplifier;
• wherein said differential input amplifier further includes an input buffer that is inserted between said input port and said input differential pair of transistors;
• and further including a diode bridge inserted between one side of said input buffer and said input differential pair of transistors to limit currents of said input buffer.

A comparator having an input signal port and an output signal port and responsive to a latch signal, comprising:

• an input buffer formed by first and second transistors with first and second control structures that define said input signal port;
• an input differential pair of of third and fourth transistors that is responsive to said input buffer;
• a differential output amplifier coupled between said input differential pair and said output signal port;
• a first biasing network that responds to one of said first and second control structures and generates a first bias signal that is coupled through said differential output amplifier to said fourth transistor of said differential pair;
• a second biasing network that is responsive to said third transistor of said input differential pair and generates a second bias signal that is coupled to one of said first and second transistors;
• and
• a latch which receives said latch signal and, in response, maintains a current state of said differential output amplifier.

A comparator having an input signal port and an output signal port and responsive to a latch signal, comprising:

• a differential input amplifier which includes an input differential pair of transistors having first and second control structures that form said input signal port;
• a differential output amplifier that is coupled to said input differential pair and said output signal port;
• a clamp coupled to limit an input signal level on at least one of said first and second control structures;
• and
• a latch which receives said latch signal and, in response, maintains a current state of said differential output amplifier;
• wherein said latch includes:
• a) a first latch differential pair of transistors that each have a current structure and a control structure cross-coupled across said output signal port;
• and
• b) a second latch differential pair arranged to switch a current between said input differential pair and said first latch differential pair in response to said latch signal.