SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof

A method of forming a layout for an SRAM device having a doped semiconductor substrate with STI trench isolation regions in said substrate filled with STI isolation material, source regions, drain regions, active areas, a wordline conductor and contacts comprising:

• forming said active areas in a doped semiconductor substrate with 90.degree. transitions in critical locations,
• forming a dielectric layer above said active areas,
• forming said wordline conductor polysilicon above said active areas transverse to said active areas,
• forming source regions in said active areas juxtaposed with said wordline conductor to form pass gate transistors while simultaneously forming drain regions in said active areas juxtaposed with said wordline conductor on the opposite side from said source regions to form pass gate transistors,
• said source region sidewalls being formed along the <100>
• crystal plane,
• forming said contacts to said drain regions between said wordline conductor extending down through to said dielectric layer to said drain regions, and
• said source regions and said drain regions having similar sizes and shapes.