Programmable wide-range frequency synthesizer
AssigneeAltera Corporation
InventorsJoseph Huang, Xiaobao Wang, Chiakang Sung, Bonnie I. Wang, Khai Nguyen, Wayne Yeung, In Whan Kim
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Abstract
Method and circuitry for a frequency synthesizer having wide operating frequency range. The frequency synthesizer uses multiple programmable loadable counters in a phase-locked loop arrangement to generate any combination of clock frequencies based on user programmed values. In a specific embodiment of the invention, the phase-locked loop includes a voltage-controlled oscillator with a built-in programmable phase shift. The present invention further provides a preferred embodiment for a high speed loadable down counter for use in the frequency synthesizer.
Claims17
A frequency synthesizer comprising:
- a phase detector having a first input coupled to receive an input signal, a second input and an output;
- a controlled-delay oscillator (CDO) having an input coupled to the output of the phase detector, and a plurality of CDO outputs configured to supply a respective plurality of CDO signals having varying delays with respect to each other;
- a programmable selection circuit having a plurality of inputs respectively coupled to the plurality of CDO outputs;
- a loop frequency divider having an input coupled to receive a first selected CDO signal, and an output coupled to the second input of the phase detector;
- and
- an output frequency divider having an input coupled to receive a second selected CDO signal, and an output coupled to carry an output signal.
A frequency divider circuit comprising:
- a loadable down counter;
- next state logic coupled to the down counter;
- a multiplexing circuit having a first plurality of inputs respectively coupled to a plurality of outputs of the next state logic, a second plurality of inputs, and a plurality of outputs coupled to a respective plurality of inputs of the down counter;
- and
- a cycle selection circuit having a plurality of outputs respectively coupled to the second plurality of inputs of the multiplexing circuit,
- wherein, during counting by the down counter, the multiplexing circuit supplies the outputs of the next stage logic to the down counter, and when the down counter reaches the end of count, the multiplexing circuit supplies the outputs of the cycle selection circuit to the down counter.
A method for dividing the frequency of a signal comprising the steps of:
- (a) applying the signal to a down counter;
- (b) storing a first count value and a second count value in memory;
- (c) loading the down counter with the first count value;
- (d) detecting when the down counter counts to the end of the first count value;
- (e) toggling an output signal when the down counter reaches end of count for the first count value;
- (f) loading the down counter with the second count value when the down counter reaches end of count for the first count value;
- (g) toggling the output signal when the down counter-reaches end of count for the second count value;
- and
- (h) repeating steps (c) through (f).
Dependencies are inferred from the claim text.