Radiation hardened six transistor random access memory and memory device

A radiation hardened storage cell, comprising:

• a first inverter including a first PFET and a first NFET having commonly coupled gates and separate drains, the drain of said first PFET including a P+ drain diffusion in an NWELL with a portion of the gate overlying the P+ drain diffusion;
• a second inverter including a second PFET and a second NFET having commonly coupled gates and separate drains, the drain of said second PFET including a P+ drain diffusion in an NWELL with a portion of the gate overlying the P+ drain diffusion;
• first and second resistors coupling the P+ drain diffusions of the first and second PFETs respectively to the drains of the first and second NFETs;
• a first pass gate PFET having a drain coupled to the commonly coupled gates of said first inverter and the P+ drain diffusion of said second PFET;
• and
• a second pass gate PFET having a drain coupled to the commonly coupled gates of said second inverter and the P+ drain diffusion of said first PFET.

A memory device, comprising:

• addressing circuitry;
• an array of word lines and complementary bit line pairs coupled to the addressing circuitry;
• a plurality of storage cells located at the intersection of selected word lines and bit line pairs;
• a sense amplifier coupled to the complementary bit line pairs;
• and
• wherein each of said plurality of storage cells comprises:
• a first inverter including a first PFET and a first NFET having commonly coupled gates and separate source/drain regions, the source/drain region of said first PFET including a P+ drain diffusion in an NWELL with a portion of the gate overlying the P+ drain diffusion;
• a second inverter including a second PFET and a second NFET having commonly coupled gates and separate source/drain regions, the source/drain region of said second PFET including a P+ drain diffusion in an NWELL with a portion of the gate overlying the P+ drain diffusion;
• first and second resistors coupling the P+ drain diffusions of the first and second PFETs respectively to the source/drain regions of the first and second NFETs;
• a first pass gate PFET having a source/drain region coupled to the commonly coupled gates of said first inverter and the P+ drain diffusion of said second PFET;
• and
• a second pass gate PFET having a source/drain region coupled to the commonly coupled gates of said second inverter and the P+ drain diffusion of said first PFET.

An apparatus, comprising:

• an electronic system;
• and
• a memory device coupled to said electronic system, wherein said memory device includes a radiation hardened storage cell, having:
• a first inverter including a first PFET and a first NFET having commonly coupled gates and separate source/drain regions, the source/drain region of said first PFET including a P+ drain diffusion in an NWELL with a portion of the gate overlying the P+ drain diffusion;
• a second inverter including a second PFET and a second NFET having commonly coupled gates and separate source/drain regions, the source/drain region of said second PFET including a P+ drain diffusion in an NWELL with a portion of the gate overlying the P+ drain diffusion;
• first and second resistors coupling the P+ drain diffusions of the first and second PFETs respectively to the source/drain regions of the first and second NFETs;
• a first pass gate PFET having a source/drain region coupled to the commonly coupled gates of said first inverter and the P+ drain diffusion of said second PFET;
• and
• a second pass gate PFET having a source/drain region coupled to the commonly coupled gates of said second inverter and the P+ drain diffusion of said first PFET.

A method of operating a radiation hardened storage cell comprising:

• sustaining a SEU event particle hit on a node of the storage cell which changes the logic state at the output of an inverter of the storage cell;
• recovering from a critical charge deposited on the storage cell as a result of the SEU event on the node;
• and
• increasing RC delay slowing feedback propagation through cross-coupled inverter pair allowing more time for recovery wherein write cycle time is not appreciably affected.