Timing circuit that selectively triggers on a rising or falling input signal edge

A method of generating an output pulse in response to an input pulse of an input signal, the method comprising:

• selectively entering a mode of a plurality of modes in response to a mode signal, the plurality of modes including a rising edge mode in which the output pulse is triggered by a rising edge of the input pulse, and including a falling edge mode in which the output pulse is triggered by a falling edge of the input pulse;
• providing at a first node a first node signal that is dependent on the input signal;
• providing at a second node a second node signal as a logic function of the first node signal, the output pulse being generated as a function of the logic levels of the first and second node signals;
• providing a logic circuit coupled to receive the mode signal and the first node signal, the logic circuit comprising:
• a delay circuit;
• a first logic gate having a first input lead coupled to the delay circuit and having an output lead coupled to the second node;
• an inverter coupled to the first node and the delay circuit;
• a second logic gate having a first input lead coupled to the inverter, an output lead coupled to the first logic gate, and a second input lead being coupled to receive an inverted version of the mode signal, and further wherein the logic circuit for:
• (a) generating a leading edge of the output pulse in response to a leading edge of the first node signal;
• and
• (b) generating a falling edge of the output pulse in response to the mode signal and the leading edge of the first node signal after a predetermined time delay, the predetermined time delay being selectively configured to be greater than a time period between a falling edge of the first node signal and a subsequent rising edge of the first node signal.

A structure for generating an output pulse in response to an input pulse of an input signal, the structure comprising:

• means for selectively entering a mode of a plurality of modes in response to a mode signal, the plurality of modes including a rising edge mode in which the output pulse is triggered by a rising edge of the input pulse, and including a falling edge mode in which the output pulse is triggered by a falling edge of the input pulse the plurality of modes including a rising edge mode and a falling edge mode;
• means for providing a first node signal at a first node the first node signal being a function of the input signal;
• means for providing at a second node a second node signal as a logic function of the first node signal, the output pulse being generated as a function of the logic levels of the first and second node signals;
• means for providing a logic circuit coupled to receive the mode signal and the first node signal, the logic circuit comprising:
• a delay circuit;
• a first logic gate having a first input lead coupled to the delay circuit and having an output lead coupled to the second node;
• an inverter coupled to the first node and the delay circuit;
• a second logic gate having a first input lead coupled to the inverter, an output lead coupled to the first logic gate, and a second input lead being coupled to receive an inverted version of the mode signal, and further wherein the logic circuit comprising:
• (a) means for generating a leading edge of the output pulse in response to a leading edge of the first node signal;
• and
• (b) means for generating a falling edge of the output pulse in response to the mode signal and the leading edge of the first node signal after a predetermined time delay, the means for generating a falling edge being selectively configured to cause the predetermined time delay to be greater than a time period between a falling edge of the first node signal and a subsequent rising edge of the first node signal.