Integrated circuit data latch driver circuit

A synchronous memory pulse generator comprising:

• a clock signal generator circuit coupled to receive a first clock signal and provide a plurality of phase shifted output signals including a second clock signal that is 90 degrees out-of-phase with the first clock signal and a third clock signal that is 180 degrees out-of-phase with the first clock signal;
• and
• a pulse generator circuit coupled to the clock signal generator circuit for providing first and second output signals having corresponding transitions spaced apart by one-half of a period of the first clock signal, the pulse generator circuit comprising:
• a first pass gate coupled to receive the first clock signal and provide the first output signal on a first output node which is coupled to a drain of a first pulldown transistor, the first pass gate being controlled by the second clock signal;
• a second pass gate coupled to receive the third clock signal and provide the second output signal on a second output node which is coupled to a drain of a second pulldown transistor, the second pass gate being controlled by the second clock signal.

A synchronous memory device pulse generator circuit with minimal output signal skew comprising:

• a first signal propagation path defined by a first inverter coupled to receive an inverted first clock signal, an output of the first inverter is coupled to an input of a first pass gate, an output of the first pass gate being coupled to an input of a second inverter and a drain of a first pulldown transistor;
• and
• a second signal propagation path defined by a third inverter coupled to receive a second clock signal which is 90 degrees out of phase with the first clock signal, an output of the third inverter being coupled to an input of a second pass gate, an output of the second pass gate being coupled to an input of a fourth inverter and a drain of a second pulldown transistor;
• wherein the first pass gate is enabled by the second clock signal and the first pulldown transistor is activated by an inverted second clock signal, the second pass gate is enabled by the inverted first clock signal and the second pulldown transistor is activated by the first clock signal.

A synchronous memory device pulse generator circuit with minimal output signal skew and duty cycle correction comprising:

• a first signal propagation path defined by a first inverter coupled to receive a first clock signal, an output of the first inverter is coupled to an input of a first pass gate, an output of the first pass gate being coupled to a drain of a first pulldown transistor;
• and
• a second signal propagation path defined by a second inverter coupled to receive a second clock signal which is 180 degrees out of phase with the first clock signal, an output of the second inverter being coupled to an input of a second pass gate, an output of the second pass gate being coupled to a drain of a second pulldown transistor;
• wherein the first pass gate is enabled by an inverse of a third clock signal which is 90 degrees out of phase with the first clock signal and the first pulldown transistor is activated by the third clock signal, the second pass gate is enabled by the third clock signal and the second pulldown transistor is activated by the inverse third clock signal.