Method for forming a hard mask of half critical dimension
AssigneeWorldwide Semiconductor Manufacturing Corp.
InventorsKung Linliu, Bor-Wen Chan
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Abstract
The present invention discloses a method for forming hard mask of half critical dimension on a substrate. A substrate is provided for the base of integrated circuits. A silicon oxide layer is formed on the substrate. A photoresist layer is formed on the silicon oxide layer and it is has a critical dimension, which the conventional lithography process can make. Subsequently, a hard mask of half critical dimension is formed in the silicon oxide layer by using the photoresist layer as an etching mask. After the oxide hard mask is formed, the gate structure of half critical dimension is formed by using the oxide hard mask.
Claims16
A method for forming an oxide hard mask of half critical dimension on a semiconductor substrate, comprising:
- forming a silicon oxide layer on said semiconductor substrate;
- defining a photoresist pattern of a critical dimension on said silicon oxide layer;
- forming a first polymer layer on said photoresist pattern and on said silicon oxide layer, wherein said first polymer layer has a thickness of half critical dimension;
- removing said first polymer layer on a top surface of said photoresist layer and said silicon oxide layer;
- etching said silicon oxide layer using said first polymer layer and said photoresist layer as an etching mask;
- removing said photoresist pattern;
- forming a second polymer layer on said first polymer layer, on said silicon oxide layer and on said semiconductor substrate, wherein said second polymer layer has a thickness of quarter critical dimension;
- removing said second polymer layer on a top surface of said silicon oxide layer;
- and
- etching said silicon oxide layer using said first polymer layer and said second polymer layer as an etching mask to form an oxide hard mask of half critical dimension on said substrate.
A method for forming an oxide hard mask of half critical dimension on a semiconductor substrate, comprising:
- forming a silicon oxide layer on said semiconductor substrate;
- defining a photoresist pattern of a critical dimension on said silicon oxide layer, wherein said photoresist pattern has a space of a critical dimension;
- forming a first polymer layer on sidewalls of said photoresist pattern, on a top surfaces of said photoresist pattern and on a top surface of said silicon oxide layer, wherein said first polymer layer has a thickness of half critical dimension;
- removing said first polymer layer on said top surface of said photoresist layer and said silicon oxide layer;
- etching said silicon oxide layer using said first polymer layer and said photoresist layer as an etching mask;
- removing said photoresist pattern;
- forming a second polymer layer on a surface of said first polymer layer, on said top surface of said silicon oxide layer and on said semiconductor substrate, wherein said second polymer layer has a thickness of quarter critical dimension;
- removing said second polymer layer on said top surface of said silicon oxide layer;
- and
- etching said silicon oxide layer by using said first polymer layer and said second polymer layer as an etching mask to form an oxide hard mask of half critical dimension on said substrate.
A method of forming an oxide hard mask of half critical dimension on a semiconductor substrate, comprising:
- forming a silicon oxide layer on said substrate;
- forming a polysilicon layer on said silicon oxide layer;
- defining a photoresist pattern on said polysilicon layer, wherein said photoresist pattern has a line width of a critical dimension;
- etching said polysilicon layer by using said photoresist pattern as a hard mask to form polysilicon islands of half critical dimension on said silicon oxide layer;
- forming spacers on sidewalls of said polysilicon islands, wherein said spacers has a thickness of half critical dimension;
- removing said polysilicon islands, wherein said spacers having a line width of half critical dimension;
- and
- etching said silicon oxide layer using said spacers as an etching mask to form an oxide hard mask of half critical dimension on said substrate.
Dependencies are inferred from the claim text.