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US 6,107,853 AGranted
Sense amplifier based flip-flop
AssigneeTexas Instruments Incorporated
InventorsBorivoje Nikolic, Wenyan Jia
Life of this patent
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Abstract
A flip-flop including a first stage and a second stage. The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and Q. These signals have equal rising and falling transitions with the same delays for the Q signal and the Q signal. The second stage has symmetrical pull-up and pull-down circuits.
Claims5
A flip-flop circuit comprising:
- a first stage for receiving data and generating monotonous transitions of S and R signals;
- a second stage for receiving said S and R signals and generating a Q output signal and Q output signal;
- and
- said second stage implementing Q=S+RQ' and Q=R.multidot.(S+Q') equations such that wherein said Q output signal and said Q output signal have equal rising and falling transitions with the same delays for said Q output signal and said Q output signal.
1 more element
Dependencies are inferred from the claim text.