US 6,103,562 AGranted

Method of making semiconductor device with decreased channel width and constant threshold voltage

AssigneeLG Semicon Co., Ltd.

InventorsJeong Hwan Son, Young Gwan Kim

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Abstract

Semiconductor device and method for fabricating the same, is disclosed, which can maintain a threshold voltage constant despite of decreased channel width, the device including a first, and a second conductive type wells in a substrate, a first, and a second gate insulating films on the first, and the second conductive type wells, a first gate electrode on the first gate insulating film, the first gate electrode being doped with a second conductive type except for edges of the first gate electrode in a channel width direction counter doped with a first conductive type, a second gate electrode on the second gate insulating film, the second gate electrode being doped with a first conductive type except for edges of the second gate electrode in a channel width direction counter doped with a second conductive type, and isolating regions formed between the first, and second conductive type wells, the first, and second gate insulating films, and the first, and second gate electrodes.

Claims7

Dependent claims

A method for fabricating a semiconductor device, comprising the steps of:

(1) forming first, and second conductive type wells in prescribed regions of a substrate, respectively;
(2) forming a first insulating film on the first, and second conductive type wells;
(3) depositing an undoped semiconductor layer on the first insulating film;
(4) injecting ions into the semiconductor layer on the first conductive type well, to form a second conductive type semiconductor layer;
(5) injecting ions into the semiconductor layer on the second conductive type well, to form a first conductive type semiconductor layer;
(6) forming a second insulating film of prescribed patterns on the first, and second conductive type semiconductor layers;
(7) forming a first conductive type counter doping region on the second conductive type semiconductor layer under edges in a direction of a channel width and both sides of the second insulating film of the prescribed pattern on the second conductive type semiconductor layer;
(8) forming a second conductive type counter doping region on the first conductive type semiconductor layer under edges in a direction of a channel width and both sides of the second insulating film of the prescribed pattern on the first conductive type semiconductor layer;
(9) etching exposed portions of the first insulating film, and the first, and second counter doping regions using the second insulating film on the first, and second conductive wells as a mask to form first, and second gate electrodes, and the first, and second gate insulating films respectively, and etching exposed portions of the first, and second conductive type well to form trenches;
(10) forming isolating and insulating films in the trenches;
and,
(11) removing the second insulating film.

9 more elements

Dependencies are inferred from the claim text.