US 6,093,594 A · CMOS optimization method utilizing sacrificial sidewall spacer

Abstract

An ultra-large scale CMOS integrated circuit semiconductor device is processed after the formation of the gates and gate oxides by N-type dopant implantation to form N-type shallow source and drain extension junctions. Spacers are formed for N-type dopant implantation to form N-type deep source and drain junctions. A higher temperature rapid thermal anneal then optimizes the NMOS source and drain extension junctions and junctions, and the spacers are removed. A thin oxide spacer is used to displace P-type dopant implantation to P-type shallow source and drain extension junctions. A nitride spacer is then formed for P-type dopant implantation to form P-type deep source and drain junctions. A second lower temperature rapid thermal anneal then independently optimizes the PMOS source and drain junctions independently from the NMOS source and drain junctions.

Claims20

Dependent claims

A method for manufacturing a semiconductor device after forming polysilicon gates and gate oxides over a semiconductor substrate, comprising the steps of:

implanting first shallow extension junctions with a first dopant;
forming first sidewall spacers on a first set of the polysilicon gates;
implanting first deep junctions with said first dopant;
rapid thermal annealing said first deep junctions whereby said first deep junctions are optimized;
removing said first sidewall spacers from the first set of the polysilicon gates;
forming thin sidewall spacers around a second set of the polysilicon gates;
implanting second shallow extension junctions with a second dopant using said thin sidewall spacers;
forming second sidewall spacers around the second set of the polysilicon gates;
implanting second deep junctions with said second dopant;
and
rapid thermal annealing said second deep junctions whereby said second deep junctions are optimized independent of the optimization of said first deep junctions.

8 more elements

A method for manufacturing a semiconductor device after forming polysilicon gates and gate oxides over a doped semiconductor substrate, comprising the steps of:

implanting first shallow extension junctions with a N-type dopant;
forming first sidewall spacers on a first set of the polysilicon gates;
implanting first deep junctions with said N-type dopant;
rapid thermal annealing said first deep junctions whereby said first deep junctions are optimized;
removing said first sidewall spacers from the polysilicon gates;
forming thin sidewall spacers around a second set of the polysilicon gates;
implanting second shallow extension junctions with a P-type dopant using said thin sidewall spacers;
forming second sidewall spacers around the second set of the polysilicon gates;
implanting second deep junctions with said P-type dopant;
and
rapid thermal annealing said second deep junctions whereby said second deep junctions are optimized independent of the optimization of said first deep junctions.

8 more elements

A method for manufacturing a semiconductor device after forming polysilicon gates and gate oxides over a semiconductor substrate, comprising the steps of:

implanting first shallow extension junctions with a first dopant;
forming a thin spacer over the polysilicon gates, the gate oxides, and the semiconductor substrate;
forming first sidewall spacers of a different composition from said thin spacer on said thin spacer around a first set of the polysilicon gates;
implanting first deep junctions with said first dopant;
rapid thermal annealing said first deep junctions;
removing said first sidewall spacers selectively to leave said thin spacer;
removing said thin spacer without damaging the polysilicon gates, the gate oxides, and the semiconductor substrate;
forming thin sidewall spacers around a second set of the polysilicon gates;
implanting second shallow extension junctions with a second dopant using said thin sidewall spacers;
forming second sidewall spacers around the second set of the polysilicon gates;
implanting second deep junctions with said second dopant;
and
rapid thermal annealing said second deep junctions at a lower temperature than said rapid thermal annealing of said first deep junctions.

10 more elements

Dependencies are inferred from the claim text.

CMOS optimization method utilizing sacrificial sidewall spacer

Life of this patent

CMOS optimization method utilizing sacrificial sidewall spacer

Life of this patent

Abstract

Claims20