US 6,090,651 A · Depletion free polysilicon gate electrodes

Abstract

A method of forming a supersaturated layer on a semiconductor device, where an initial phase layer is deposited on the semiconductor device. The initial phase layer has a solid phase dopant saturation level and a liquid phase dopant saturation level, where the liquid phase dopant saturation level is greater than the solid phase dopant saturation level. A concentration of a dopant is impregnated within the initial phase layers, where the concentration of the dopant is greater than the solid phase dopant saturation level and no more than about the liquid phase dopant saturation level. The initial phase layer is annealed, without appreciably heating the semiconductor device, using an amount of energy that is high enough to liquefy the initial phase layer over a melt duration. This dissolves the dopant in the liquefied initial phase layer. The amount of energy is low enough to not appreciably gasify or ablate the initial phase layer. The liquefied initial phase layer is cooled to freeze the dissolved dopant in a supersaturated, electrically activated concentration, thereby forming the supersaturated layer. An initial phase layer of either polysilicon or amorphous silicon may be deposited over a CMOS device. After laser annealing the initial phase layer with a melt duration of no more than about 100 nanoseconds, it is transformed into a doped polysilicon gate electrode that can be patterned and further processed.

Claims20

Dependent claims

A method of forming a supersaturated layer on a semiconductor device, comprising:

depositing an initial phase layer on the semiconductor device, the initial phase layer having a solid phase dopant saturation level and a liquid phase dopant saturation level, where the liquid phase dopant saturation level is greater than the solid phase dopant saturation level,
impregnating a concentration of a dopant within the initial phase layer, where the concentration of the dopant is greater than the solid phase dopant saturation level and no more than about the liquid phase dopant saturation level,
annealing the initial phase layer without appreciably heating the semiconductor device, using an amount of energy high enough to liquefy the initial phase layer over a melt duration, thereby dissolving the dopant in the liquefied initial phase layer, where the amount of energy is low enough to not appreciably gasify or ablate the initial phase layer, and
cooling the liquefied initial phase layer to freeze the dissolved dopant in a supersaturated, electrically activated concentration, thereby forming the supersaturated layer.

1 more element

A method of forming a supersaturated polysilicon gate electrode on a CMOS semiconductor device, comprising:

depositing an initial phase silicon gate layer on the CMOS semiconductor device, the initial phase silicon gate layer having a solid phase dopant saturation level and a liquid phase dopant saturation level, where the liquid phase dopant saturation level is greater than the solid phase dopant saturation level,
ion implanting a concentration of a dopant within the initial phase silicon gate layer, where the concentration of the dopant is greater than the solid phase dopant saturation level and no more than about the liquid phase dopant saturation level,
laser annealing the initial phase silicon gate layer without appreciably heating the semiconductor device, using an amount of energy high enough to liquefy the initial phase layer for no more than about 100 nanoseconds, thereby dissolving the dopant in the liquefied initial phase silicon gate layer, where the amount of energy is low enough to not appreciably gasify or ablate the initial phase silicon gate layer, and
cooling the liquefied initial phase silicon gate layer to freeze the dissolved dopant in a supersaturated, electrically activated concentration, thereby forming the supersaturated polysilicon gate electrode.

1 more element

Dependencies are inferred from the claim text.

Depletion free polysilicon gate electrodes

Life of this patent

Depletion free polysilicon gate electrodes

Life of this patent

Abstract

Claims20