Dynamic latch circuitry

A method of implementing a logical function comprising:

• generating a delayed clock signal from a clock signal, wherein a transition of the delayed clock signal follows a corresponding transition of the clock signal after a delay period;
• initializing a first node to a first state before the transition of the clock signal;
• providing data at a data input for storage before the transition of the clock signal;
• permitting a change in state at the first node during the delay period based on the data input;
• and
• storing a state of the first node during the delay period.

A logic circuit comprising:

• an initialization circuit to initialize a first node to an initialized state before a transition of a clock signal;
• a first device coupled to the initialization circuit and a data input;
• and
• an enabling circuit coupled to the first device and a delayed clock signal to enable the first device to alter the initialized state at the first node after the transition of the clock signal and before a corresponding transition in the delayed clock signal.

A logic circuit comprising:

• a data input;
• a clock input, wherein the logic circuit stores data at the data input when a transition occurs at the clock input;
• a first device coupled to the data input and an intermediate node;
• a second device in series with the first device, wherein the second device is coupled to the clock input;
• and
• a third device in series with the second device, wherein the third device is coupled to a delayed version of a signal at the clock input.