Memory array having a multi-state element and method for forming such array or cellis thereof
AssigneeMicron Technology, Inc.
InventorSteven T. Harshfield
Life of this patent
Estimating the term…
Abstract
A memory device having a plurality of memory arrays. Each array has a plurality of memory cells, each memory cell including an electrode defining a respective contact area. Each memory array is formed by depositing a continuous chalcogenide layer. This chalcogenide layer, even when continuous, will have active areas formed above the electrodes, and a conductive layer electrically coupling at least a portion of the active areas. The memory array can also include a dielectric volume surrounding at least a portion of the plurality of electrodes. The electrodes can be contacts, plugs or pillars deposited in etched openings in the dielectric volume.
Claims20
A method of forming a memory array having a plurality of memory cell areas, the method comprising the steps of:
- forming a plurality of electrodes;
- forming a continuous chalcogenide layer over said plurality of electrodes;
- and
- forming a conductive element over at least a portion of said chalcogenide layer, said conductive element contacting a plurality of said memory cell areas.
A method of forming a memory array having a plurality of memory cell areas, the method comprising the steps of:
- forming a plurality of electrodes;
- forming a continuous chalcogenide layer over said plurality of electrodes;
- forming a conductive element over at least a portion of said continuous chalcogenide layer, said conductive element contacting a plurality of said memory cell areas;
- and
- forming a volume of dielectric generally surrounding said electrodes, wherein said dielectric volume is formed prior to said step of forming said chalcogenide layer, wherein said dielectric volume is formed to define at least one trench extending above a plurality of said electrodes to define a first surface proximate said electrodes and a second surface generally removed from said electrodes.
A method of manufacture for a memory device having at least one memory array, the memory array comprising a plurality of memory cells, the method comprising the steps of:
- providing a base structure including at least one access device and having a memory array surface;
- providing at least one electrode coupled to a corresponding access device, the electrodes separated by areas of non-physical contact and distributed along the memory array surface of the base structure at selected locations, each electrode having an electrical contact area;
- depositing a continuous layer of a multi-state material over at least a portion of the memory array surface of the base structure, said layer of multi-state material configured to electrically contact the contact areas of each said electrode.
A method of manufacture for a memory array for use in an integrated circuit, the method comprising the steps of:
- providing an underlayer including a memory array area including a plurality of access devices;
- providing a plurality of electrodes placed at selected locations in the memory array area, each electrode coupled to a corresponding access device, the electrodes separated by areas of non-physical contact, each electrode having an electrical contact area;
- applying a continuous layer of a multi-state material over the memory array area, said layer of multi-state material configured to electrically contact the contact areas of each said electrode;
- and
- placing a continuous electrode material layer over a portion of the multi-state material layer, thereby creating a multi-layer stack.
A method of manufacture for a memory array for use in an integrated circuit, the method comprising the steps of:
- providing an underlayer including a memory array area including a plurality of access devices;
- providing a plurality of electrodes placed at selected locations in the memory array area, each electrode coupled to a corresponding access device, the electrodes separated by areas of non-physical contact, each electrode having an electrical contact area, wherein the step of providing the plurality of electrodes comprises the steps of:
- applying a dielectric layer over the underlayer;
- placing the electrode within the dielectric layer;
- and
- coupling the electrode to the underlayer;
- and wherein the step of placing the electrode comprises the steps of:
- etching an opening in the dielectric layer and depositing the electrode in the opening;
- etching the dielectric layer after the electrode has been deposited, leaving a portion of the electrode protruding above the surface of the dielectric layer;
- and
- applying a layer of a spacer material over the dielectric layer and etching the layer of spacer material to form side spacers surrounding the sides of the protruding portion of the electrode;
- applying a layer of a multi-state material over the memory array area, said layer of multi-state material configured to electrically contact the contact areas of each said electrode;
- and
- placing a continuous electrode material layer over a portion of the multi-state layer, thereby creating a multi-layer stack.
Dependencies are inferred from the claim text.