Pseudo silicon on insulator MOSFET device

A method of fabricating a MOSFET device, on a semiconductor substrate, using a thin silicon oxide layer to isolate a heavily doped source/drain region, from said semiconductor substrate, comprising the steps of:

• forming isolation regions in said semiconductor substrate;
• forming a silicon dioxide gate insulator layer on said semiconductor substrate;
• forming a silicon oxide capped, polysilicon gate structure, on said silicon dioxide gate insulator layer;
• forming a lightly doped source/drain region, in a region of said semiconductor substrate, not covered by said silicon oxide capped, polysilicon gate structure, or by said isolation regions;
• forming silicon oxide spacers on the sides of said silicon oxide capped, polysilicon gate structure;
• anisotropic etching of a region of said lightly doped source/drain region, and of an underlying portion of said semiconductor substrate, exposed between said silicon oxide spacers, and said isolation region, to create first openings in said semiconductor substrate, leaving lightly doped source/drain segments under said silicon oxide spacers;
• growing said thin silicon oxide layer on the exposed surfaces of said first opening;
• depositing a first intrinsic silicon layer, completely filling said first openings;
• etching of said first intrinsic silicon layer, to a level in which first silicon layer remains in the bottom portion of said first openings, resulting in second openings, located between said silicon oxide spacers, and said isolation regions, with said thin silicon oxide layer, on sides of said lightly doped source/drain segments, exposed in said second openings;
• removing said thin silicon oxide layer, from the sides of said lightly doped source/drain segments, exposed in said second openings;
• depositing a second intrinsic silicon layer, completely filling said second opening;
• etching of said second intrinsic silicon layer, to a level in which said second silicon layer is planar with the top surface of said semiconductor substrate;
• and
• forming said heavily doped source/drain regions, in said second intrinsic silicon layer, and in said first intrinsic silicon layer, with said heavily doped source/drain regions overlying said thin silicon oxide layer, in said first openings, and with said heavily doped source/drain regions, interfacing the sides of said lightly doped source/drain segments, in regions of said second openings in which said thin silicon oxide layer has been removed.