Method and apparatus for a N-nary logic circuit using 1 of N signals

A system that evaluates a N-Nary logic circuit that uses 1 of N signals with 1 of N encoding, comprising:

• a shared logic tree circuit that evaluates one or more input signals and produces an output signal;
• a first input 1 of N signal coupled to said shared logic tree circuit wherein said first input 1 of N signal comprises a first bundle of N wires routed together between different cells and use a 1 of N encoding to indicate multiple values of information conveyed by said first bundle of wires and where at most one and only one wire of said first bundle of wires is true during an evaluation cycle;
• a second input 1 of N signal coupled to said shared logic tree circuit wherein said second input 1 of N signal comprises a second bundle of N wires routed together between different cells and use a 1 of N encoding to indicate multiple values of information conveyed by said second bundle of wires and where at most one and only one wire of said second bundle of wires is true during said evaluation cycle;
• and
• an output 1 of N signal coupled to said shared logic tree circuit wherein said output 1 of N signal comprises a third bundle of N wires routed together between different cells and use a 1 of N encoding to indicate multiple values of information conveyed by said third bundle of wires and where at most one and only one wire of said third bundle of wires is true during said evaluation cycle.

A method that evaluates a N-Nary logic circuit that uses 1 of N signals with 1 of N encoding, comprising:

• receiving a first input 1 of N signal coupled to a shared logic tree circuit wherein said first input 1 of N signal comprises a first bundle of N wires routed together between different cells and use a 1 of N encoding to indicate multiple values of information conveyed by said first bundle of wires and where at most one and only one wire of said first bundle of wires is true during an evaluation cycle;
• receiving a second input 1 of N signal coupled to said shared logic tree circuit wherein said second input 1 of N signal comprises a second bundle of N wires routed together between different cells and use a 1 of N encoding to indicate multiple values of information conveyed by said second bundle of wires and where at most one and only one wire of said second bundle of wires is true during said evaluation cycle;
• evaluating said first input 1 of N signal and said second input 1 of N signal with said shared logic tree circuit;
• and
• producing an output 1 of N signal from said shared logic tree circuit's evaluation, said output 1 of N signal couples to said shared logic tree circuit wherein said output 1 of N signal comprises a third bundle of N wires routed together between different cells and use a 1 of N encoding to indicate multiple values of information conveyed by said third bundle of wires and where at most one and only one wire of said third bundle of wires is true during said evaluation cycle.

A method that provides a N-Nary logic circuit with 1 of N signals using 1 of N encoding, comprising:

• providing a shared logic tree circuit that evaluates one or more input signals and produces an output signal;
• coupling a first input 1 of N signal to said shared logic tree circuit wherein said first input 1 of N signal comprises a first bundle of N wires routed together between different cells and use a 1 of N encoding to indicate multiple values of information conveyed by said first bundle of wires and where at most one and only one wire of said first bundle of wires is true during an evaluation cycle;
• coupling a second input 1 of N signal to said shared logic tree circuit wherein said second input 1 of N signal comprises a second bundle of N wires routed together between different cells and use a 1 of N encoding to indicate multiple values of information conveyed by said second bundle of wires and where at most one and only one wire of said second bundle of wires is true during said evaluation cycle;
• and
• coupling an output 1 of N signal to said shared logic tree circuit wherein said output 1 of N signal comprises a third bundle of N wires routed together between different cells and use a 1 of N encoding to indicate multiple values of information conveyed by said third bundle of wires and where at most one and only one wire of said third bundle of wires is true during said evaluation cycle.