Single-electron floating-gate MOS memory

A data storage device, comprising:

• (a) a source-to-drain path including a channel region between a source and a drain, the channel region being comprised of a semiconductor;
• (b) a single floating gate disposed over the channel region and isolated from the channel region by a first gate dielectric layer having a thickness of about 1 nanometer, the floating gate having dimensions less than 10 nanometers by 10 nanometers by 10 nanometers for storing a single charge carrier;
• and
• (c) a control gate disposed over the floating gate and isolated from the floating gate by a second gate dielectric layer;
• wherein the channel region has a width smaller than a Debye screening length of the single charge carrier stored on the floating gate.

A data storage device, comprising:

• (a) a source-to-drain path including a channel region between a source and a drain, the channel region being comprised of a semiconductor, the channel region having a width of less than 70 nanometers;
• (b) a single floating gate disposed over the channel region and isolated from the channel region by a first gate dielectric layer having a thickness of about 1 nanometer, the floating gate having dimensions less than 10 nanometers by 10 nanometers by 10 nanometers for storing a single charge carrier;
• and
• (c) a control gate disposed over the floating gate and isolated from the floating gate by a second gate dielectric layer.

A data storage device, comprising:

• (a) a source-to-drain path including a channel region between a source and a drain, the channel region being a semiconductor, the channel region having a length from the source to the drain and also having a width;
• (b) a floating gate for storing at least one charge carrier, the floating gate being disposed over the channel region and isolated from the channel region by a first gate dielectric layer having a thickness of about 1 nanometer, the floating gate having a width, wherein the width of the floating gate is self-aligned with the width of the channel;
• and
• (c) a control gate disposed over the floating gate and isolated from the floating gate by a second gate dielectric layer.

A data storage device, comprising:

• (a) a source-to-drain path including a channel region between a source and a drain, the channel region being comprised of a semiconductor;
• (b) a floating gate for storing at least one charge carrier, the floating gate being disposed over the channel region and isolated from the channel region by a first gate dielectric layer having a thickness of about 1 nanometer, the floating gate having lateral dimensions defined by lithography;
• and
• (c) a control gate disposed over the floating gate and isolated from the floating gate by a second gate dielectric layer so that the single charge carrier on the floating gate at room temperature produces a significant shift in threshold voltage of the channel region with respect to the control gate.