Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor

A memory device, comprising:

• an array of memory cells, each cell including a vertical access transistor formed of a single crystalline semiconductor pillar that extends outwardly from a substrate with body and first and second source/drain regions, a gate disposed adjacent to only one side of the pillar adjacent to the body region and a trench capacitor wherein a first plate of the trench capacitor is integral with the second source/drain region and a second plate of the capacitor is disposed adjacent to and surrounding the first plate;
• a number of bit lines that are each selectively coupled to a number of the memory cells at the first source/drain region of the access transistor so as to fonn columns of memory cells in a folded bit line configuration;
• and
• a number of word lines disposed substantially orthogonal to the bit lines in trenches between rows of the memory cells, wherein each trench includes two word lines, each word line coupled to alternating gates on opposite sides of the trench.

A memory array comprising:

• a number of memory cells forming an array with a number of rows and columns, each memory cell including an access transistor having body and first and second source/drain regions formed vertically, outwardly from a substrate and a gate disposed adjacent to only one side of the body, the second source/drain region including an upper semiconductor surface;
• a trench capacitor, wherein the trench capacitor includes a first plate that is formed integral with the second source/drain region of the access transistor and a second plate of the trench capacitor surrounds the second source/drain of the access transistor;
• a number of first isolation trenches separating adjacent rows of memory cells;
• first and second word lines disposed in each of the first isolation trenches and coupled to alternating gates on opposite sides of the trench;
• and
• a number of second isolation trenches, each substantially orthogonal to the first isolation trenches and interposed between adjacent memory cells.