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AssigneeAdvanced Micro Devices, Inc.
InventorsDavid E. Norris, Larry D. Hewitt, Jeffrey M. Blumenthal
Estimating the term…
A register array accessible by both a system microprocessor and a digital signal processor of a PC audio circuit, comprising: (i) a random access memory (RAM) having a first port connected to a digital signal processor input/output port, and a second port connected to a RAM input/output port; (ii) a register data port connected to the RAM input/output port and having a connection to a register data bus; (iii) timing circuitry for timing the register array operations; (iv) row and column select circuitry for respectively selecting rows and columns in said RAM; and (v) an input/output channel ready signal line connected to said timing circuitry. The RAM includes a plurality of edge bits each of which stores a value indicating whether processing of a row of data values stored in said RAM is active or inactive. The system microprocessor is disabled from accessing the RAM whenever the RAM is not idle or the microprocessor seeks to access a row of the RAM currently subject to access by the digital signal processor. If the microprocessor is disabled from writing data to the RAM, the data may be temporarily stored in the register data port until the microprocessor's access is enabled.
A register array, comprising:
A register array suitable for a digital signal processor, comprising:
A register array, comprising:
A register array suitable for a digital signal processor, comprising:
A register array suitable for a digital signal processor, comprising:
A register array accessible by both a computer system microprocessor and a digital signal processor comprising:
A method of using a register array, which is accessible by both a microprocessor of a host computer and a digital signal processor, to control accesses by said microprocessor and said digital signal processor of a random access memory (RAM) contained in said register array, wherein said RAM comprises rows and columns, comprising:
A method of using a register array, accessible by both a microprocessor of a host computer system and a digital signal processor, to control accesses by said microprocessor and said digital signal processor of a random access memory (RAM) contained in said register array, the method comprising:
A method of using a register array, which is accessible by both a microprocessor of a host computer and a digital signal processor, to control accesses by said microprocessor and said digital signal processor of a random access memory (RAM) contained in said register array, wherein said RAM comprises rows, columns, and a plurality of status bits, comprising:
Dependencies are inferred from the claim text.