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US 6,040,583 AGranted
Electron beam exposure method using a moving stage
AssigneeNEC Corporation
InventorNaka Onoda
Life of this patent
Estimating the term…
Abstract
An electron beam exposure system has a continuous stage drive for driving a stage at a constant speed. Area of a semiconductor chip is divided into an array of unit meshes to calculate pattern density in each mesh. A group of meshes having an equal density level is combined as a sub-strip region having dimensions equal to or lower than the maximum width determined based on the ability of the electron beam exposure system.
Claims6
An electron beam exposure method comprising the steps of:
- dividing a semiconductor chip into a plurality of sub-strip regions each having a width equal to or lower than a maximum width determined by an electron beam deflection range, at least two of said sub-strip regions having different widths;
- and
- consecutively exposing said plurality of sub-strip regions to form desired patterns on said semiconductor chip,
- wherein each said sub-strip region is modified based on sub-strip regions used in exposure during exposure for underlying patterns.
1 more element
An electron beam exposure method comprising the steps of:
- dividing a semiconductor chip into a plurality of sub-strip regions each having a width equal to or lower than a maximum width determined by an electron beam deflection range, at least two of said sub-strips regions having different widths;
- and
- consecutively exposing said plurality of sub-strip regions to form desired patterns on said semiconductor chip,
- wherein said width of each sub-strip is determined based on a pattern density in said each sub-strip region.
1 more element
An electron beam exposure method comprising the steps of:
- dividing a semiconductor chip into a plurality of sub-strip regions each having a width equal to or lower than a maximum width determined by an electron beam deflection range, at least two of said sub-strips regions having different widths;
- dividing the semiconductor chip into an array of unit meshes;
- calculating a pattern density level in each of said unit meshes;
- and
- consecutively exposing said plurality of sub-strip regions to form desired patterns on said semiconductor chip.
2 more elements
Dependencies are inferred from the claim text.