Post metal code engineering for a ROM

A method of forming a semiconductor device comprising the steps of:

• a) providing a partially completed semiconductor device having a peripheral area and a cell area over a semiconductor substrate;
• at least a word line and bit lines over said cell area;
• transistors comprising at least a gate electrode, a source region, and a drain region over said peripheral area;
• b) forming a first dielectric layer overlying said word line, said first dielectric layer composed of borophosphosilicate glass;
• said first dielectric layer having a thickness in a range of between about 5000 and 7000 .ANG.;
• c) forming contact openings to said source and drain regions in said peripheral area;
• d) reflowing said first dielectric layer;
• e) forming a ROM mask having mask ROM openings over portions of said word lines in said cell area;
• f) etching a thickness of said first dielectric layer overlying said word line in said cell area through said ROM mask openings;
• the remaining first dielectric layer having a thickness in a range of between about 2000 and 4000 .ANG.;
• g) removing said ROM mask;
• h) forming a first metal layer over said cell area and peripheral area;
• i) patterning said first metal layer forming first level metal contacts to said source and drain regions in said peripheral areas and removing said first metal layer over said cell area;
• j) forming a second dielectric layer over said first dielectric layer;
• said second dielectric layer composed of a PE-oxide layer having a thickness in a range of between about 1000 and 3000 .ANG.;
• the remaining first dielectric layer and second dielectric layer have a combined thickness ranging between about 3000 .ANG. and 7000 .ANG.;
• k) storing said semiconductor device;
• l) forming a code mask having code mask openings over portions of said word lines in said cell area;
• m) performing a code implant in said cell area by implanting impurities through said code mask openings, said first and second dielectric layers and through at least a portion of said word line, forming a code implant region in said semiconductor substrate;
• and
• n) annealing said implant semiconductor device to activate said implanted impurities in said code implant region thereby programming said semiconductor device, said code implant is performed at an energy in a range of between about 300 Kev and 360 KeV and a dose in a range of between about 1E14 and 3E14 atom/cm2 and uses Boron ions with a double absolute charge.

A method of manufacturing an integrated circuit device comprising the steps of:

• a) providing a partially completed semiconductor device having a peripheral area and a cell area over a semiconductor substrate;
• at least a word line and bit lines over said cell area;
• transistors comprising at least a gate electrode, a source region, and a drain region over said peripheral area;
• b) forming a first dielectric layer overlying said cell area and said peripheral area, said first dielectric layer compose of BPSG having a thickness in a range of between about 5000 and 7000 .ANG.;
• c) forming a ROM mask having ROM mask openings over portions of said cell area;
• d) etching said first dielectric layer overlying cell area through said ROM mask openings;
• e) forming contact openings through said first dielectric layer exposing said source region and said drain region in said peripheral area;
• f) forming a first metal layer over said cell area and peripheral area;
• g) patterning said first metal layer forming metal contacts to said source and drain regions, and removing said first metal layer over said cell area;
• h) forming metal contacts to said source and drain regions in said peripheral area;
• i) forming a second dielectric layer over said first dielectric layer and said metal contacts;
• said second dielectric layer composed of oxide formed using a plasma enhanced process and having a thickness in a range of between about 1000 and 7000 .ANG.;
• j) forming a code mask having code mask openings over portions of said word lines in said cell area;
• k) performing a code implant in said cell area by implanting impurities through said code mask openings, said first and second dielectric layers and through at least a portion of said gate electrode thus, forming a code implant region in said semiconductor substrate;
• and
• l) annealing said implant semiconductor device to activate said implanted impurities in said code implant region thereby programming said semiconductor device, said code implant is performed at an energy in a range of between about 300 Kev and 360 KeV and a dose in a range of between about 1E14 and 3E14 atom/cm2 and uses Boron ions with a double absolute charge.