Up/down counter
AssigneeLG Semicon Co., Ltd.
InventorByung-Doo Kim
Life of this patent
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Abstract
The counter of the present invention includes an input unit, a sampling unit and a determiner unit. The input unit receives a plurality of control signal including a mode selection signal, a clock signal and a reset signal. The sampling unit receives output signals of the input unit based on the clock signal and reset signal. The sampling unit has a plurality of latches and generating a plurality of first output signals and the adjacent latch of the plurality of latches are coupled to each other. The determiner unit is coupled to the sampling unit to receive the plurality of first output signals and is coupled to the input unit to receive an output signal based on the mode selection signal. The determiner unit outputs a plurality of count signals indicative of a count value, which is incremented or decremented based on the mode selection signal.
Claims11
A counter comprising:
- an input unit receiving a plurality of control signals including a mode selection signal, a clock signal and a reset signal;
- a sampling unit receiving output signals of said input unit based on the clock signal and reset signal, said sampling unit having a plurality of latches and generating a plurality of first output signals and a plurality of second output signals, said plurality of latches being coupled to each other;
- and
- a determiner unit coupled to said sampling unit to receive the plurality of first output signals and coupled to said input unit to receive output signals of the input unit based on the mode selection signal, said determiner unit outputting a plurality of count signals indicative of count values, which are incremented or decremented based on the mode selection signal.
Dependencies are inferred from the claim text.