US 6,014,586 AGranted

Vertically integrated semiconductor package for an implantable medical device

AssigneePacesetter, Inc.

InventorsAlvin H. Weinberg, Buehl E. Truex

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Abstract

An electronic package having vertically integrated components placed upon a substrate surface is configured to increase packing density of the components. Integrated circuits which are vertically-stacked and attached to the substrate surface communicate with surrounding components through connection to bond pads on the substrate surface. The bond pads can be placed entirely about a perimeter of the integrated circuits to achieve optimal packing density. Individual bond pads may be shared by two or more integrated circuits by connection therewith. In an alternative embodiment, a separate integrated circuit is attached to the substrate adjacent to the stacked integrated circuits with a row of shared bond pads positioned therebetween. Individual passive or active components may be placed between bond pads for incorporation into the circuit structure.

Claims18

Dependent claims

An implantable cardiac stimulation device, comprising:

electronic circuitry for generating cardiac stimulation pulses in at least one of the absence or presence of certain cardiac events, said electronic circuitry comprising:
a first integrated circuit chip having a first array of signal contact pads disposed thereon;
a second integrated circuit chip having a second array of signal contact pads disposed thereon;
a substrate having a first predefined die-attach area located on a surface of said substrate, said first integrated circuit chip being mounted on said first predefined die-attach area on said surface, said substrate also having a first plurality of bond pads located thereon adjacent said first predefined die-attach area, said second integrated circuit chip being vertically stacked upon said first integrated circuit chip;
a first plurality of wirebonds, each one of said first plurality of wirebonds extending between a selected one of said first array of signal contact pads to a selected one of said first plurality of bond pads providing electrical communication therebetween;
a second plurality of wirebonds, each one of said second plurality of wirebonds extending between a selected one of said second array of signal contact pads to a selected one of said first plurality of bond pads providing electrical communication therebetween, wherein at least one of said first plurality of bond pads is commonly shared by one of said first plurality of wirebonds and at least one of said second plurality of wirebonds whereby electrical comminication is enabled between said first and second integrated circuit chips via said shared bond pads in said first plurality of bond pads;
at least one additional circuit component extending between and electrically connected to two of said bond pads in said first pluralities of bond pads;
and
a housing for hermetically sealing said electronic circuitry therein.

6 more elements

An implantable cardiac stimulation device, comprising:

electronic circuitry for generating cardiac stimulation pulses in at least one of the absence or presence of certain cardiac events, said electronic circuitry comprising:
a first integrated circuit chip having a first array of signal contact pads disposed thereon;
a second integrated circuit chip having a second array of signal contact pads disposed thereon;
a third integrated circuit chip having a third array of signal contact pads disposed thereon;
a substrate having adjacent first and second predefined die-attach areas located on a surface of said substrate, said substrate also having a first plurality of bond pads located thereon adjacent said first predefined die-attach area and a second plurality of bond pads located thereon adjacent said second predefined die-attach area, said first and second pluralities of bond pads together comprising a single row of bond pads located between said first and second predefined die-attach areas and common to said first and second pluralities of bond pads, said first integrated circuit chip being mounted on said first predefined die-attach area on said surface of said substrate, said second integrated circuit chip being vertically stacked upon said first integrated circuit, chip and said third integrated circuit chip being mounted on said second predefined die-attach area on said surface of said substrate;
a first plurality of wirebonds, each one of said first plurality of wirebonds extending between a selected one of said signal contact pads on said first array of signal contact pads to a selected one of said bond pads on said common row of bond pads providing electrical connection therebetween;
a second plurality of wirebonds, each one of said second plurality of wirebonds extending between a selected one of said signal contact pads on said second array of signal contact pads to a selected one of said bond pads on said common row of bond pads providing electrical connection therebetween;
a third plurality of wirebonds, each one of said third plurality of wirebonds extending between a selected one of said signal contact pads on said third array of signal contact pads to a selected one of said bond pads on said common row of bond pads providing electrical connection therebetween, wherein at least one of said bond pads on said common row of bond pads is commonly shared by at least two wirebonds from said first, second and third pluralities of wirebonds whereby electrical communication is enabled between at least two of said first, second and third integrated circuit chips via said shared bond pads;
at least one additional circuit component extending between and electrically connected to two of said bond pads on said first and second pluralities of bond pads;
and
a housing for hermetically sealing said electronic circuitry therein.

8 more elements

An implantable cardiac stimulation device, comprising:

electronic circuitry for generating cardiac stimulation pulses in at least one of the absence or presence of certain cardiac events, said electronic circuitry comprising:
a substrate having adjacent first and second predefined die-attach areas located on a surface of said substrate, said substrate having a row of bond pads located on the substrate and positioned between said first and second die-attach pads;
a first integrated circuit chip having a first array of signal contact pads disposed thereon, said first integrated circuit chip being mounted on said first predefined die-attach area on said surface of said substrate;
a first plurality of wirebonds, each one of said first plurality of wirebonds extending between a selected one of said signal contact pads on said first array of signal contact pads to a selected one of said bond pads on said row of bond pads providing electrical connection therebetween;
a second integrated circuit chip having a second array of signal contact pads disposed thereon, said second integrated circuit chip being vertically stacked upon said first integrated circuit chip;
a second plurality of wirebonds, each one of said second plurality of wirebonds extending between a selected one of said signal contact pads on said second array of signal contact pads to a selected one of said bond pads on said row of bond pads providing electrical connection therebetween, wherein at least one of said bond pads is commonly shared by one of said first plurality of wirebonds and at least one of said second plurality of wirebonds whereby electrical communication is enabled between said first and second integrated circuit chips via said shared bond pads;
a third integrated circuit chip having a third array of signal contact pads disposed thereon, said third integrated circuit chip being mounted on said second predefined die-attach area on said surface of said substrate;
a third plurality of wirebonds, each one of said third plurality of wirebonds extending between a selected one of said signal contact pads on said third array of signal contact pads to a selected one of said bond pads on said row of bond pads providing electrical communication therebetween;
a fourth plurality of wirebonds, each one of said third plurality of wirebonds extending between a selected one of said signal contact pads on one of said first or second arrays of signal contact pads to a selected one of said bond pads on said row of bond pads providing electrical communication therebetween and enabling electrical communication to between said third integrated circuit chip and at least one of said first and second integrated circuit chips;
at least one additional circuit component extending between and electrically connected between two of said first or second bond pads located on said substrate;
and
a housing for hermetically sealing said electronic circuitry therein.

9 more elements

An implantable cardiac stimulation device, comprising:

electronic circuitry for generating cardiac stimulation pulses in at least one of the absence or presence of certain cardiac events, said electronic circuitry comprising:
a first integrated circuit chip having a first array of signal contact pads disposed thereon;
a second integrated circuit chip having a second array of signal contact pads disposed thereon;
a substrate having adjacent first and second predefined die-attach areas located on a surface of said substrate, said substrate also having a first plurality of bond pads located thereon adjacent said first predefined die-attach area and a second plurality of bond pads located thereon adjacent said second predefined die-attach area, said first and second pluralities of bond pads together comprising a single row of bond pads located between said first and second predefined die-attach areas and common to said first and second pluralities of bond pads, said first integrated circuit chip being mounted on said first predefined die-attach area on said surface of said substrate, and said second integrated circuit chip being mounted on said second predefined die-attach area on said surface of said substrate;
a first plurality of wirebonds, each one of said first plurality of wirebonds extending between a selected one of said first arrays of signal contact pads to a selected one of said first plurality of bond pads providing electrical communication therebetween;
a second plurality of wirebonds, each one of said second plurality of wirebonds extending between a selected one of said signal contact pads on said second array of signal contact pads to a selected one of said second plurality of bond pads providing electrical communication therebetween, wherein at least one of said bond pads is common to said first and second pluralities of bond pads and is commonly shared by one of said first plurality of wirebonds and at least one of said second plurality of wirebonds whereby electrical communication is enabled between said first and said integrated circuit chips via said shared bond pads;
at least one additional circuit component extending between and electrically connected to two of said bond pads on said first and second plurality of bond pads;
and
a housing for hermetically sealing said electronic circuitry therein.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/806,364Filed 27 Feb 1997 · continuation
Priority: 20 Nov 1995
Granted: 11 Jan 2000
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

A61N 1/3758
Constructional arrangements, e.g. casings: packaging of the components within the casing
A61N 1/375
Arrangements in connection with the implantation of stimulators: constructional arrangements, e.g. casings
H10W 90/00
Package configurations
H10W 72/5449
Dispositions of bond wires: not being orthogonal to a side surface of the chip, e.g. fan-out arrangements

Family

Serial560,920Parent of this continuation · filed 20 Nov 1995
US 6,014,586 AThis patent

From the US filing history. Foreign family members aren’t listed.

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