Differential current switch logic gate
AssigneeIntel Corporation
InventorsDinesh Somasekhar, Kaushik Roy, Junji Sugisawa
Life of this patent
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Abstract
A differential current switch logic (DCSL) system is provided which has an evaluation tree including a plurality of input terminals and a pair of complementary output nodes. The DCSL system also has an output network which establishes a pair of state outputs at a predetermined level during a precharge phase and establishes the state outputs at complementary levels in response to the evaluation tree output nodes during an evaluate phase. First and second NMOS transistors are connected in series between the DCVS output state network and the evaluation tree output nodes with their gates coupled to the state outputs to isolate the outputs from the evaluation tree following evaluation.
Claims17
A differential current switch logic circuit comprising:
- an evaluation tree including a plurality of input terminals and first and second output nodes;
- an output network having first and second state outputs, the output network establishing both state outputs at a predetermined level during a precharge phase and providing a path to ground for one of the state outputs in response to the evaluation tree output nodes to establish the state outputs at complementary levels during an evaluate phase;
- first and second evaluation transistors clocked by an evaluation clock signal, in which each state output is cross-coupled to drive the other output during the evaluate phase initiated by the evaluation clock signal;
- a first isolation transistor coupled between the output network and one of the evaluation tree output nodes, the first isolation transistor having its gate coupled to the second state output;
- a second isolation transistor coupled between the output network and the other complementary evaluation tree output node, the second isolation transistor having its gate coupled to the first state output;
- and
- during the evaluate phase, one of the first or second isolation transistors isolates a non-grounded complementary output node of the evaluation tree from the output network.
A differential current switch logic circuit comprising:
- an evaluation tree including a plurality of input terminals and first and second output nodes for output of complementary states;
- first and second sense transistor pairs, each pair being coupled in series between a voltage supply and ground potential and having their gates coupled together, wherein first and second state outputs are defined at respective junctions of the first and second sense transistor pairs
- first and second evaluation transistors clocked by an evaluation clock signal during an evaluate phase, in which the first state output is coupled to the gates of the second sense transistor pair through the first evaluation transistor and the second state output is coupled to the gates of the first sense transistor pair through the second evaluation transistor.
A differential current switch logic circuit comprising:
- an evaluation tree including a plurality of input terminals and a pair of complementary output nodes;
- means for generating first and second state outputs;
- means for establishing the first and second state outputs at a predetermined level during a precharge phase;
- means for clocking a cross-coupling of the state outputs and coupling to nodes of the evaluation tree during the evaluate phase;
- means for evaluating signals on the input terminals during the evaluate phase to generate complementary state outputs.
A differential current switch logic circuit comprising:
- an evaluation tree including a plurality of input terminals and a pair of complementary output nodes;
- a pair of precharge transistors each coupled in series between a voltage supply and ground potential and being clocked by a precharge clock signal;
- first and second sense transistor pairs, each pair being coupled in series between the voltage supply and ground potential and having their gates coupled together, wherein first and second state outputs are defined at respective junctions of the first and second sense transistor pairs;
- first and second evaluation transistors clocked by an evaluation clock signal which is complementary to the precharge clock signal;
- the first state output being coupled to the gates of the second sense transistor pair through the first evaluation transistor and the second state output being coupled to the gates of the first sense transistor pair through the second evaluation transistor;
- a first isolation transistor coupled between the first evaluation transistor and one of the evaluation tree output nodes, the first isolation transistor having its gate coupled to the second state output;
- and
- a second isolation transistor coupled between the second evaluation transistor and the complementary evaluation tree output node, the second isolation transistor having its gate coupled to the first state output.
A method of providing complementary state outputs responsive to an evaluation tree which provides one path to ground in response to a plurality of inputs thereto, the state outputs being selectively isolated from the evaluation tree by a pair of switchable isolation devices coupled therebetween, the method comprising:
- providing an output network including a pair of state outputs;
- precharging both state outputs to a predetermined precharge level during a precharge phase;
- maintaining the precharge level by feeding back the precharge level state outputs to the isolation devices;
- establishing complementary evaluation levels at the state outputs by providing a path to ground through the evaluation tree by clocking an initiation of an evaluate phase for determining the path to ground for one of the state outputs, the output state being isolated from driving the output network until clocked in the evaluate phase;
- isolating the other non-grounded complementary path by decoupling the non-grounded path by the use of one of the isolation devices.
Dependencies are inferred from the claim text.