US 6,002,708 A · Spread spectrum localizers

Abstract

A network of localizers determines relative locations in three-dimensional space to within 1 cm by cooperatively measuring propagation times of pseudorandom sequences of electromagnetic impulses. Ranging transmissions may include encoded digital information to increase accuracy. The propagation time is determined from a correlator circuit which provides an analog pseudo-autocorrelation function sampled at discrete time bins. The correlator has a number of integrators, each integrator providing a signal proportional to the time integral of the product of the expected pulse sequence delayed by one of the discrete time bins, and the non-delayed received antenna signal. With the impulses organized as doublets the sampled correlator output can vary considerably in shape depending on where the autocorrelation function peak falls in relation to the nearest bin. Using pattern recognition the time of arrival of the received signal can be determined to within a time much smaller than the separation between bins. Because operation of standard CMOS circuitry generates noise over a large frequency range, only low-noise circuitry operates during transmission and reception. To provide the time accuracy necessary for distancing, a high-frequency clock operates during inter-localizer communications. The high-frequency clock uses a phase-lock loop circuit to increase the clock rate and a programmable delay to provide still finer time graduations. A stage in the low-frequency clock uses low-noise circuitry during transmissions and receptions, and standard circuitry at other times.

Claims30

Dependent claims

An apparatus for determining a sub-chip length accuracy time-of-arrival of a received impulse sequence, comprising:

means for generating a digital integration sequence resembling said received impulse sequence;
means for generating a plurality of delayed integration sequences from said integration sequence;
means for integrating each of said delayed integration sequences multiplied by said received impulse sequence to provide a series of output values approximating a time sampling of a correlation function between said integration sequence and said received impulse sequence;
first means for determining a first location of a maximum of said output values;
and
second means for determining a second location of a peak of said correlation function to an accuracy of less than a time between chips of said digital integration sequence using said location of said maximum of said output values and magnitudes of said output values on both sides of said maximum.

3 more elements

An apparatus for determining multiple values of a correlation function of an analog signal and a digital signal at a set of evaluation times, comprising:

a shift register array, said digital signal being shifted through said shift register array from a first shift register to a last shift register on a sequence of shift pulses applied thereto, said shift register array having a plurality of taps to generate a plurality of delayed digital signals, said delayed digital signals being delayed by a plurality of delay times;
means for directing a first bit of said digital sequence to said first shift register of said shift register array at a starting time such that said time of arrival of said analog signal is not later than an exit of said first bit of said digital sequence from said last register of said shift register array;
and
a plurality of integrators, said delayed digital signals from said taps in said shift register array being directed to said integrators where said delayed digital signals are multiplied by said analog signal to provide analog integrator outputs approximating values of said correlation function of said analog signal and said digital signal sampled at said evaluation times.

1 more element

An apparatus for determining values of a correlation function of an analog signal and a digital signal at a set of evaluation times, comprising:

a shift register array, said digital signal being shifted through said shift register array on a sequence of shift pulses applied thereto, said shift register array having a plurality of taps to generate a plurality of delayed digital signals, said delayed digital signals being delayed by a plurality of delay times;
and
a plurality of integrators, said delayed digital signals from said taps in said shift register array being directed to said integrators where said delayed digital signals are multiplied by said analog signal to provide analog integrator outputs equivalent to values of said correlation function of said analog signal and said digital signal sampled at said evaluation times, each of said integrators including:
a transconductance amplifier for converting a differential voltage at a pair of input terminals to an output current at a pair of output terminals;
a first switching network applying a positive polarity version of said analog signal to said input terminals of said transconductance amplifier when one of said delayed digital signals directed to said one of said integrators has said first value, and applying a negative polarity version of said analog signal to said input terminals of said transconductance amplifier when said one of said delayed digital signals has said second value;
an integration capacitor for storing an integration charge produced by said output current from by said transconductance amplifier;
and
a means for reading said integration charge on said integration capacitor.

5 more elements

Dependencies are inferred from the claim text.

Spread spectrum localizers

Life of this patent

Spread spectrum localizers

Life of this patent

Abstract

Claims30