Crisscross voltage level shifter

A voltage level shifter comprising:

• a pull-down circuit having a first cascode amplifier and a second cascode amplifier, where an inverted signal is applied to an input of the first cascode amplifier and a non-inverted signal is applied to an input of the second cascode amplifier, for pulling down an output signal to a first predefined voltage level;
• said first cascode amplifier comprises a first transistor having a gate, a source, and a drain and a second transistor having a gate, a source and a drain, where said source of said first transistor is coupled to said first predefined voltage level, said gate of said first transistor is coupled to said inverted signal, the drain of said first transistor is connected to the source of said second transistor, the drain of said second transistor is connected to a crisscross pull-up circuit and the gate of said second transistor is coupled to a predefined power supply having a third predefined voltage level;
• said second cascode amplifier comprises a third transistor having a gate, a source, and a drain and a fourth transistor having a gate, a source and a drain, where said source of said third transistor is coupled to said first predefined voltage level, said sate of said third transistor is coupled to said non-inverted signal, the drain of said third transistor is connected to the source of said fourth transistor, the drain of said fourth transistor is connected to said crisscross pull-up circuit and the gate of said fourth transistor is coupled to said predefined power supply having said third predefined voltage level;
• said crisscross pull-up circuit, is coupled to said pull-down circuit, for pulling up an output signal to a second predefined voltage level when said pull-down circuit is not pulling down said output signal to said first predefined level;
• and
• a feedforward circuit, coupled to said pull-down circuit, for providing feedforward signals to said output of said first and second cascode amplifiers that are derived from the input signals of said first and second cascode amplifiers, wherein said feedforward circuit comprises a fifth transistor having a source, drain and gate, where said rate of said fifth transistor is coupled to the inverted signal, said source is coupled to said drain of said fourth transistor, and said drain is coupled to said third predefined voltage level;
• and a sixth transistor having a source, drain and gate, where said rate of said sixth transistor is coupled to said non-inverting signal, said source is connected to the drain of said second transistor, and said drain is coupled to said third predefined voltage level.