US 6,002,270 A · Synchronous differential logic system for hyperfrequency operation

Abstract

A synchronous differential logic system is provided for implementation of pipelined computational structures capable of hyperfrequency operation. An individual logic circuit has a differential cascode switch and a synchronous sense amplifier which operates as a latch. A plurality of differential inputs are connected to the differential cascode switch which produces complementary signals at first and second nodes. The cascode switch is connected to the synchronous sense latch which provides complementary output signals of the logic circuit. The synchronous sense latch comprises an equalization transistor and two cross-coupled inverters, each connected to first and second power supply buses. The equalization transistor is connected to the first and second outputs, of the logic gate and to a global system clock. The two output signals of the logic circuit are forced by the equalization transistor to a voltage approximately equal to one half of the power supply voltage in one clock phase and are partially released by the equalization transistor in the second clock phase. The synchronous sense latch output is a function of the differential logic inputs applied to the cascode switch. High speed of operation is also accomplished by a) reducing logic signal voltage swings, b) using a synchronous sense latch which is not disconnected from the power supply during equalization, and c) forcing the terminals of each bistable circuit to a substantially sensitive operating point which is one half of the power supply voltage, before the bistable circuit switches to valid logic levels.

Claims37

Dependent claims

A synchronous differential logic circuit, comprising:

a continuous power source having first and second terminals;
a synchronous latching sense amplifier including a first inverter having an input and output, a second inverter having an input coupled to the output of the first inverter and output coupled to the input of the first inverter, and an equalization switch for coupling together the outputs of the first and second inverters, each of said first and second inverters being connected directly across the first and second terminals of the continuous power source so that said first and second inverters draw current from said continuous power source when the outputs of the first and second inverters are coupled together by the equalization switch;
and
a differential switch for coupling one of the inputs of the first and second inverters to one of the terminals of the continuous power source in response to a differential input.

1 more element

A synchronous differential logic system, comprising:

a synchronous differential logic circuit having:
first and second power supply terminals,
a clock input terminal for receiving a clock signal,
first and second differential data input terminals for receiving complementary data input signals,
first and second differential data output terminals for producing complementary data output signals in response to said complementary data input signals,
a differential logic switch connected between said differential data input terminals and said differential data output terminals for providing a conduction path between one of said differential output terminals and said second power supply terminal in response to said complementary data input signals,
a first inverting amplifier having an input connected to said first differential data output terminal and an output connected to said second differential output terminal, a first power port directly connected to said first power supply terminal, and a second power port directly connected to said second power supply terminal,
a second inverting amplifier having an input connected to said second differential data output terminal, and an output connected to said first differential data output terminal, a first power port directly connected to said first power supply terminal, and a second power port directly connected to said second power supply terminal, and
a clocked device having a first electrode connected to said first differential data output terminal, a second electrode connected to said second differential data output terminal, and a third electrode connected to said clock input terminal for providing a conduction path between said first electrode and said second electrode in response to a clock signal applied at said third electrode;
and
a continuous power source connected directly across the first and second power supply terminals of the synchronous differential logic circuit so that said first and second amplifying inverters draw current from the continuous power source when a conduction path between the first and second electrodes of the clocked device is provided the clock signal applied to the third electrode.

8 more elements

A synchronous differential logic system, comprising:

a synchronous differential logic circuit having:
first and second power supply terminals,
a clock input terminal for receiving a clock signal;
first and second differential data input terminals for receiving complementary data input signals,
first and second differential data output terminals for producing complementary data output signals in response to said complementary data input signals,
a differential logic switch having third and fourth output terminals for providing a conduction path between one of said third and fourth output terminals and said second power supply terminal in response to said complementary data input signals,
a first inverting amplifier having an input connected to said first differential data output terminal, an output connected to said second differential data output terminal, a first power port directly connected to said first power supply terminal, and a second power port directly connected to said second power supply terminal,
a second inverting amplifier having an input connected to said second differential data output terminal, an output connected to said first differential data output terminal, a first power port directly connected to said first power supply terminal, and a second power port directly connected to said second power supply terminal,
a clocked device having a first electrode connected to said first differential data output terminal, a second electrode connected to said second differential data output terminal, and a third electrode connected to said clock input terminal for providing a conduction path between said first electrode and said second electrode in response to a clock signal applied at said third electrode, and
first and second NFETs, each NFET having source and drain electrodes defining ends of a conductivity path and a gate electrode for controlling the conductivity of the path, said drain of said first NFET being connected to said first differential data output terminal, the source of said first NFET being connected to third output terminal of the differential logic switch, the gate of said first NFET being connected to said second differential data output terminal, the drain of said second NFET being connected to said second differential data output terminal, the source of said second NFET being connected to said fourth output terminal of the differential logic switch, and the gate of said second NFET being connected to said first differential data output terminal;
and
a continuous power source connected directly across the first and second power supply terminals of the synchronous differential logic circuit so that said first and second amplifying inverters draw current from the continuous power source when a conduction path between the first and second electrodes of the clocked device is provided by the clock signal applied to the third electrode.

9 more elements

A synchronous differential logic system, comprising:

a synchronous differential logic circuit having:
first and second power supply terminals,
a clock input terminal for receiving a clock signal;
first and second differential data input terminals for receiving complementary data input signals;
first and second differential data output terminals for producing complementary data output signals in response to said complementary data input signals;
a differential logic switch having third and fourth output terminals for providing a conduction path between one of said third and fourth output terminals and said second power supply terminal in response to said complementary data input signals;
a first inverting amplifier having an input connected to said first differential data output terminal, an output connected to said second differential data output terminal, a first power port directly connected to said first power supply terminal, and a second power port directly connected to said second power supply terminal;
a second inverting amplifier having an input connected to said second differential data output terminal, an output connected to said first differential data output terminal, a first power port directly connected to said first power supply terminal, and a second power port directly connected to said second power supply terminal;
a clocked device having a first electrode connected to said first differential data output terminal, a second electrode connected to said second differential data output terminal, and a third electrode connected to said clock input terminal for providing a conduction path between said first electrode and said second electrode in response to a clock signal applied at said third electrode;
a first transmission line having an end connected to the third output terminal of the differential logic switch;
a second transmission line having an end connected to the fourth output terminal of the differential logic switch;
first and second NFETs, each NFET having source and drain electrodes defining ends of a conductivity path and a gate electrode for controlling the conductivity of the path, said drain of said first NFET being connected to said first differential data output terminal, the source of said first NFET being connected to the other end of said first transmission line, the gate of said first NFET being connected to said second differential data output terminal, the drain of said second NFET being connected to said second differential data output terminal, the source of said second NFET being connected to the other end of the second transmission line, and the gate of said second NFET being connected to said first differential data output terminal;
and
a continuous power source connected directly across the first and second power supply terminals of the synchronous differential logic circuit so that said first and second amplifying inverters draw current from the continuous power source when a conduction path between the first and second electrodes of the clocked device is provided by the clock signal applied to the third electrode.

11 more elements

Dependencies are inferred from the claim text.

Synchronous differential logic system for hyperfrequency operation

Life of this patent

Synchronous differential logic system for hyperfrequency operation

Life of this patent

Abstract

Claims37