ROM device having shaped gate electrodes and corresponding code implants

A ROM having NAND type memory cells, comprising:

• a silicon substrate provided with a background doping of a first type impurity;
• a depletion layer of a second type impurity adjacent a surface of said substrate;
• a gate oxide layer on the surface of said substrate;
• a plurality of spaced elongated first gate electrodes of polycrystalline silicon on said gate oxide layer, said first electrodes each having a thickness in the range of 2000 to 4000 Angstroms, a width in the range of 0.3 to 0.8 micrometers and an elongated central depression;
• a plurality of elongated second gate electrodes of polycrystalline silicon on said gate oxide layer, said plurality of elongated second gate electrodes positioned alternately between said plurality of spaced elongated first gate electrodes, said second gate electrodes each having an elongated central depression;
• and
• code implant regions doped with the first type impurity in said depletion layer of said substrate and located centrally of said first and second electrodes in registry with said central depressions, said code implant regions not extending laterally beyond said first and second electrodes.

A ROM having NAND type memory cells, comprising:

• a silicon substrate provided with a background doping of a first type impurity;
• a depletion layer of a second type impurity adjacent a surface of said substrate;
• a gate oxide layer on the surface of said substrate;
• a plurality of spaced elongated first gate electrodes of polycrystalline silicon on said gate oxide layer, said first electrodes each having an elongated central depression;
• a plurality of elongated second gate electrodes of polycrystalline silicon on said gate oxide layer, said plurality of elongated second gate electrodes positioned alternately between said plurality of spaced elongated first gate electrodes, said second gate electrodes each having an elongated central depression;
• a layer of polysilicon oxide separating the first gate electrodes from the second gate electrodes;
• and
• code implant regions doped with the first type impurity in said depletion layer of said substrate and located centrally of said first and second electrodes in registry with said central depressions, said code implant regions not extending laterally beyond said first and second electrodes.

A ROM having NAND type memory cells, comprising:

• a silicon substrate provided with a background doping of a first type impurity;
• a depletion layer of a second type impurity adjacent a surface of said substrate;
• a gate oxide layer on the surface of said substrate;
• a plurality of spaced elongated first gate electrodes of polycrystalline silicon on said gate oxide layer, said first electrodes each having a thickness in the range of 2000 to 4000 Angstroms, a width in the range of 0.3 to 0.8 micrometers and an elongated central depression;
• a plurality of elongated second gate electrodes of polycrystalline silicon on said gate oxide layer, said plurality of elongated second gate electrodes positioned alternately between said plurality of spaced elongated first gate electrodes, said second gate electrodes each having an elongated central depression;
• and
• code implant regions self-alignedly doped with the first type impurity in said depletion layer of said substrate and located centrally of said first and second electrodes in registry with said central depressions, said code implant regions not extending laterally beyond said first and second electrodes.

A ROM having NAND type memory cells, comprising:

• a silicon substrate provided with a background doping of a first type impurity;
• a depletion layer of a second type impurity adjacent a surface of said substrate;
• a gate oxide layer on the surface of said substrate;
• a plurality of spaced elongated first gate electrodes of polycrystalline silicon on said gate oxide layer, said first electrodes each having an elongated central depression;
• a plurality of elongated second gate electrodes of polycrystalline silicon on said gate oxide layer, said plurality of elongated second gate electrodes positioned alternately between said plurality of spaced elongated first gate electrodes, said second gate electrodes each having an elongated central depression;
• a layer of polysilicon oxide separating the first gate electrodes from the second gate electrodes;
• and
• code implant regions self-alignedly doped with the first type impurity in said depletion layer of said substrate and located centrally of said first and second electrodes in registry with said central depressions, said code implant regions not extending laterally beyond said first and second electrodes.