Method of making chip mountings and assemblies

A bonding tape for making a plurality of semiconductor assemblies, said tape comprising a dielectric layer having a plurality of units, each said unit including:

• (a) a central region at least partially bounded by at least one slot in said dielectric layer;
• (b) a peripheral region disposed outside of the at least one slot;
• (c) at least one bridge connecting the central region to the peripheral region;
• (d) a plurality of terminals disposed on the central region;
• and
• (e) a plurality of leads extending from the terminals to the slots, each of said leads extending partially across one of said slots so that each said lead is detached from the peripheral region and deformable by bending out of a plane of said dielectric layer.

A bonding component for making semiconductor assemblies including:

• (a) a dielectric layer having a plurality of slots in said dielectric layers;
• (b) a central region of said dielectric layer substantially surrounded by said slots;
• (c) a peripheral region of said dielectric layer disposed outside said slots;
• (d) at least one bridge connecting the central region to the peripheral region;
• (e) a plurality of terminals disposed on the central region;
• and
• (f) a plurality of leads extending from the terminals to the slots, each said lead extending partially across one of said slots so that each said lead is detached from the peripheral region and deformable by bending out of a plane of said dielectric layer.

A method of making a connection component for a semiconductor assembly comprising the steps of:

• (a) providing a dielectric layer having a central region, one or more slots disposed adjacent the central region and a peripheral region disposed adjacent the slots opposite the central region;
• (b) providing a metallic structure including a plurality of terminals disposed on said central region, one or more plating bus runs disposed on said peripheral region, and leads extending from said terminals to said plating bus runs;
• (c) applying a resist to said leads in zones adjacent said plating bus runs and plating regions of said leads outside of said zones with an etch-resistant metal;
• and
• (d) removing said resist and etching said leads so as to form gaps in said leads.

A method of forming a semiconductor connection component comprising the steps of:

• (a) providing a dielectric layer with a slot therein;
• (b) providing a metallic structure including terminals disposed on the dielectric layer on one side of the slot, a plating bus line disposed on the other side of the slot, and leads extending from the terminals across the slot to the plating bus;
• (c) applying resist to said leads in zones adjacent to said plating bus;
• (d) plating the leads with a bonding material using the plating bus to conduct plating current to the leads, the plating step depositing the bonding material at least on portions of the leads aligned with the slot;
• and
• (e) removing said resist and etching said leads in said zones to form gaps.

A method of making a connection component for a semiconductor assembly comprising the steps of:

• (a) providing a dielectric layer;
• (b) forming an aperture in said dielectric layer;
• (c) providing a metallic structure including a plurality of terminals disposed on said dielectric layer, a plurality of leads connected to said terminals and extending at least partially across said aperture, and a plating bus interconnecting each lead of said plurality of leads;
• (d) applying a resist to said metallic structure such that each lead is separated from the others by a zone covered by said resist;
• (e) plating regions of said leads not covered by said resist;
• and
• (f) removing said resist and etching unplated regions of said metallic structure to form gaps in said metallic structure and to disconnect said leads from one another.

A bonding component for making semiconductor assemblies, including:

• (a) a dielectric layer having a top surface with first and second regions on opposite sides of an aperture in said dielectric layer;
• (b) a plurality of terminals disposed on said first region;
• and
• (c) a plurality of leads having first ends on said first region connected to said terminals and having second ends extending in a plane of said top surface partially across said aperture;
• wherein said leads are plated by a process of applying a plating current through a temporary connection between said second ends of said leads and a plating bus on said second region, and then removing said temporary connection.