CCD type semiconductor device

Abstract

The disclosure relates to charge-coupled devices taking the form of shift registers and, more specifically, to those working in the MPP (Multi-Pinned Phase) mode, i.e. with high negative polarisation of the electrodes during the phases of waiting or of integration of integration of the photosensitive charges. These registers use a potential barrier created by a P type compensating implantation in a zone 16 located beneath a first electrode of each stage of the register. This barrier separates the stages from one another. To increase the charge storage capacity during the storage phase and the charge transfer capacity during the transfer, it is provided that the compensating implantation of the zone 16 will extend beneath only one part (and not the totality) of the first electrode of each stage of the register. Application to photosensitive image sensors, analog delay lines, charge-coupled analog memories, working in MPP mode during the waiting phases to limit losses of information due to the dark current. FIG. 4.

Dependencies are inferred from the claim text.