Shallow trench isolation formation with improved trench edge oxide
AssigneeAdvanced Micro Devices, Inc.
InventorsNick Kepler, Olov Karlsson, Larry Wang, Basab Bandyopadhyay, Effiong Ibok, Christopher F. Lyons
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AssigneeAdvanced Micro Devices, Inc.
InventorsNick Kepler, Olov Karlsson, Larry Wang, Basab Bandyopadhyay, Effiong Ibok, Christopher F. Lyons
Estimating the term…
A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges. Embodiments include forming a photoresist mask directly on a pad oxide layer which, in turn, is formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. After masking, the substrate is etched to form a trench, an oxide liner is grown in the trench surface, and a polish stop layer is deposited over the oxide liner and the pad oxide layer. The polish stop layer is then masked to the trench edges, and the polish stop in the trench etched away. The trench is then filled with an insulating material, the insulating material is planarized, and the polish stop is removed by etching. Thus, the oxide liner is allowed to grow on the trench edges without the restraint of a polish stop, resulting in a thick, rounded oxide on the trench edges. Additionally, no polish stop layer remains in the trench to cause unwanted electrical effects.
A method of manufacturing a semiconductor device having an insulated trench formed in a semiconductor substrate or in an epitaxial layer on the semiconductor substrate, which method comprises:
A method of manufacturing a semiconductor device having an insulated trench formed in a semiconductor substrate or in an epitaxial layer on the semiconductor substrate, which method comprises:
A method of manufacturing an integrated circuit on a semiconductor substrate, which method comprises:
Dependencies are inferred from the claim text.