US 5,970,359 AGranted

Method of forming a capacitor for DRAM

AssigneeUnited Microelectronics Corp.

InventorChaun-Fu Wang

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Abstract

A method of forming a capacitor for DRAM according to the invention is disclosed. The method includes the follow steps: a dielectric layer, an etching stop layer, a first insulating layer, a first conductive layer and a second insulating layer are formed in order on a substrate. A contact hole is formed in the second insulating layer. the first conductive layer, the first insulating layer, the etching stop layer and the dielectric layer. Then, a second conductive layer is formed over the substrate and completely fills the contact hole. The second conductive layer is patterned. Next, a silicon nitride layer is formed adjacently to the patterned second conductive layer. Parts of the second insulating layer and the first conductive layer are removed by using the silicon nitride layer as a mask, thereby exposing parts of the first insulating layer. Afterwards, a third conductive layer is formed over the substrate. Parts of the third conductive layer on the silicon nitride layer and parts of the first insulating layer are removed. Thereafter, the silicon nitride layer, the remaining second insulating layer, the first insulating layer are removed to expose a part of a lower electrode consisting of the remaining first, second and third conductive layers.

Claims19

Dependent claims

A method of forming a capacitor for DRAM comprising the steps of:

providing a substrate having a field effect transistor with source/drain regions formed thereon;
forming a first dielectric layer, an etching stop layer, a first insulating layer, a first conductive layer and a second insulating layer in order on the substrate;
forming a contact hole in the second insulating layer, the first conductive layer, the first insulating layer, the etching stop layer and the first dielectric layer by patterning, thereby exposing one of the source/drain regions;
forming a second conductive layer over the substrate, the second conductive layer completely filling the contact hole to electrically connect the one of the source/drain regions;
removing parts of the second conductive layer by patterning;
forming a third insulating layer adjacent to both vertical sides of the patterned second conductive layer;
removing parts of the second insulating layer and the first conductive layer to expose parts of the first insulating layer by using third insulating layer as a mask;
forming a third conductive layer over the substrate;
removing parts of the third conductive layer on the third insulating layer and parts of the first insulating layer to expose the third insulating layer and the parts of the first insulating layer;
removing the third insulating layer, the remaining second insulating layer and the first insulating layer to expose a part of a lower electrode consisting of the remaining first, second and third conductive layers by etching;
forming a second dielectric layer on the surface of the exposed part of the lower electrode;
and
forming a fourth conductive layer over the substrate to completely cover the second dielectric layer.

10 more elements

A method of forming a capacitor for DRAM comprising the steps of:

providing a substrate having a field effect transistor with source/drain regions formed thereon;
forming a first dielectric layer, a first silicon nitride layer, a first silicon oxide layer, a first polysilicon layer and a second silicon oxide layer in order on the substrate;
forming a contact hole in the second silicon oxide layer, the first polysilicon layer, the first silicon oxide layer, the first silicon nitride layer and the first dielectric layer by patterning, thereby exposing one of the source/drain regions;
forming a second polysilicon layer over the substrate, the second polysilicon layer completely filling the contact hole to electrically connect the one of the source/drain regions;
removing parts of the second polysilicon layer by patterning;
forming a second silicon nitride layer adjacent to both vertical sides of the patterned second polysilicon layer;
removing parts of the second silicon oxide layer and the first polysilicon layer to expose parts of the first silicon oxide layer by using the second silicon nitride layer as a mask;
forming a third polysilicon layer over the substrate;
removing parts of the third polysilicon layer on the second silicon nitride layer and parts of the first silicon oxide layer to expose the second silicon nitride layer and the parts of the first silicon oxide layer;
removing the second silicon nitride layer by using the second silicon oxide layer as an etching stop layer;
removing the remaining second silicon oxide layer, the first silicon oxide layer to expose a part of a lower electrode consisting of the remaining first, second and third polysilicon layers by using the first silicon nitride layer as an etching stop layer;
forming a second dielectric layer on the surface of the exposed part of the lower electrode;
and
forming a fourth polysilicon layer over the substrate to completely cover the second dielectric layer.

11 more elements

Dependencies are inferred from the claim text.