Method of making a plug transistor

A method of making an IGFET, comprising the steps of:

• providing a semiconductor substrate with an active region of a first conductivity type;
• implanting a doped layer of a second conductivity type in the active region;
• depositing a dielectric layer over the doped layer;
• forming a masking layer over the dielectric layer;
• etching a portion of the dielectric layer beneath an opening in the masking layer using the masking layer as an etch mask, thereby forming an opening in the dielectric layer above a portion of the doped layer;
• implanting a dopant of the first conductivity type through the opening in the dielectric layer into the portion of the doped layer using the masking layer as an implant mask, thereby converting the portion of the doped layer into the first conductivity type and splitting the doped layer into source and drain regions;
• removing the masking layer;
• forming a source in the source region and a drain in the drain region, wherein the doped layer provides essentially all doping of the second conductivity type for the source and the drain;
• forming a gate insulator on the active region and in the opening in the dielectric layer;
• depositing a gate material over the dielectric layer and into the opening in the dielectric layer and on the gate insulator;
• and
• polishing the gate material so that a portion of the gate material over the dielectric layer is removed and a remaining portion of the gate material in the opening in the dielectric layer forms a gate that contacts the dielectric layer and the gate insulator.

A method of making complementary transistors, comprising the steps of:

• providing a semiconductor substrate with a first active region of a first conductivity type and a second active region of a second conductivity type;
• implanting a first doped layer of the second conductivity type in the first active region;
• implanting a second doped layer of the first conductivity type in the second active region;
• depositing a dielectric layer over the first and second active regions;
• forming a first masking layer over the dielectric layer, wherein the first masking layer includes an opening above a portion of the first active region and the first masking layer covers all of the second active region;
• etching a portion of the dielectric layer beneath the opening in the first masking layer using the first masking layer as an etch mask, thereby forming a first opening in the dielectric layer above a portion of the first doped layer;
• implanting a dopant of the first conductivity type through the first opening in the dielectric layer into the portion of the first doped layer using the first masking layer as an implant mask, thereby converting the portion of the first doped layer into the first conductivity type and splitting the first doped layer into first source and drain regions in the first active region;
• forming a first source in the first source region and a first drain in the first drain region, wherein the first doped layer provides essentially all doping of the second conductivity type for the first source and the first drain;
• forming a first gate insulator on the first active region and in the first opening;
• depositing a first gate material over the dielectric layer and into the first opening and on the first gate insulator;
• polishing the first gate material so that a portion of the first gate material over the dielectric layer is removed and a remaining portion of the first gate material in the first opening forms a first gate that contacts the dielectric layer and the first gate insulator;
• forming a second masking layer over the dielectric layer, wherein the second masking layer includes an opening above a portion of the second active region and the second masking layer covers all of the first active region;
• etching a portion of the dielectric layer beneath the opening in the second masking layer using the second masking layer as an etch mask, thereby forming a second opening in the dielectric layer above a portion of the second doped layer;
• implanting a dopant of the second conductivity type through the second opening in the dielectric layer into the portion of the second doped layer using the second masking layer as an implant mask, thereby converting the portion of the second doped layer into the second conductivity type and splitting the second doped layer into second source and drain regions in the second active region;
• forming a second source in the second source region and a second drain in the second drain region, wherein the second doped layer provides essentially all doping of the first conductivity type for the second source and the second drain;
• forming a second gate insulator on the second active region and in the second opening;
• depositing a second gate material over the dielectric layer and into the second opening and on the second gate insulator;
• and
• polishing the second gate material so that a portion of the second gate material over the dielectric layer is removed and a remaining portion of the second gate material in the second opening forms a second gate that contacts the dielectric layer and the second gate insulator.