Method and structure for optimizing the performance of a semiconductor device having dense transistors
AssigneeAdvanced Micro Devices, Inc.
InventorsJon Cheek, Daniel Kadosh, Derick J. Wristers
Life of this patent
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AssigneeAdvanced Micro Devices, Inc.
InventorsJon Cheek, Daniel Kadosh, Derick J. Wristers
Estimating the term…
A method and structure for optimizing the performance of a semiconductor device having dense transistors. A method consistent with the present invention includes forming a first test structure on a first substrate portion. The first test structure includes a transistor having a gate electrode formed at a design width and at a first line spacing similar to the line spacing of a dense transistor. One or more electrical properties the transistor of the first test structure is measured. A second test structure is formed on a second substrate portion. The second test structure includes a transistor having a gate electrode formed at the same design width as the transistor of the first test structure and at a second line spacing greater than the first line spacing. One or more electrical properties of the transistor of the second test structure are measured. Using the measured one or more electrical properties, one or more relationships are developed between the measured one or more electrical properties and the transistors at the first line spacing and the second line spacing.
A method of forming a test structure for use in determining a relationship between a transistor electrical property and transistor density, comprising:
A method of determining one or more relationships between one or more electrical properties and transistors density, comprising:
A method of determining a transistor electrical property to density relationship, comprising:
A method of forming a semiconductor structure for use in determining a relationship between a transistor electrical property and transistor density, comprising:
Dependencies are inferred from the claim text.