Nonvolatile memory array with NAND string memory cell groups selectively connected to sub bit lines
AssigneeSony Corporation
InventorKenshiro Arase
Life of this patent
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Abstract
A semiconductor nonvolatile memory device where a main bit line is divided into a plurality of sub bit lines via operational connecting means, memory transistors connected to the sub bit lines are arranged in the form of a matrix, and control gate electrodes of these memory transistors are connected to word lines, provided with a means for setting sub bit lines at a programming prohibit potential at the time of a data programming operation; a means for causing a discharge in a selected sub bit line among the sub bit lines set to the programming prohibit potential and placing the non-selected sub bit lines among the sub bit lines in a floating state; and a means for supplying a program voltage to the selected word line.
Claims19
A semiconductor nonvolatile memory device, comprising:
- a plurality of main bit lines each divided into a plurality of sub bit lines via selective connecting means,
- a plurality of word lines,
- a plurality of memory transistors connected to the sub bit lines and arranged in a matrix, wherein control gate electrodes of these memory transistors are each connected to one of said word lines;
- a booster circuit for selectively setting said sub bit lines at a programming prohibit potential during a data programming operation;
- and
- a memory control circuit for causing a discharge in a selected sub bit line and placing all other non-selected sub bit lines in a floating state, during said data programming operation;
- wherein said memory control circuit then supplies a program voltage to a selected word line.
A method of data programming of a NAND type semiconductor nonvolatile memory device wherein a plurality of main bit lines are each divided into a plurality of sub bit lines via operational connecting means, serial strings of memory transistors which are electrically programmed are connected in series between one of said sub bit lines and a ground line via selection transistors to constitute NAND strings, and the NAND strings are arranged in a matrix, the method comprising:
- selecting a sub bit line connected to a selected NAND string and boosting a potential of a channel portion of said selected NAND string to a programming prohibit potential using said selected sub bit line;
- discharging said selected sub bit line to the main bit line according to data to be programmed, while placing all non-selected sub bit lines in a floating state;
- and
- supplying a program voltage to said selected word line.
A nonvolatile memory device comprising:
- a plurality of main bit lines, wherein each main bit line is connected to a plurality of sub bit lines;
- a control connection transistor connected between each said sub bit line and a respective main bit line;
- a plurality of memory transistors arranged in groups, each such group of memory transistors comprising a plurality of memory transistors connected in series, and each such series of memory transistors beginning and ending with a selection transistor connected in series with said series of memory transistors, wherein each said sub bit line comprises a plurality of said groups of memory transistors;
- a plurality of word lines connected to gate electrodes of said memory transistors;
- and
- a plurality of selection lines connected to gate electrodes of said selection transistors.
A method of programming a nonvolatile memory device comprising:
- controlling connections between a main bit line and a plurality of sub bit lines with connection control transistors;
- controlling connections between a plurality of groups of memory transistors and each of sad sub bit lines with a selection transistor, wherein each said group of memory transistors comprises a plurality of memory transistors connected in series, said series being connected to a said selection transistor;
- controlling individual memory transistors with a plurality of word lines, each of which is connected to a gate electrode of one of said memory transistors;
- and
- controlling said selection transistors with a plurality of selection lines connected to gate electrodes of said selection transistors;
- precharging said sub bit lines with a program prohibit voltage;
- discharging only a selected sub bit line which placing all non-selected sub bit lines in a floating state;
- providing a programming voltage on a word line connected to a selected memory transistor connected to said selected sub bit line.
Dependencies are inferred from the claim text.