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US 5,969,923 AGranted
Electrostatic protection structure for MOS circuits
AssigneesSarnoff Corporation, Sharp Kabushiki Kaisha
InventorLeslie Ronald Avery
Life of this patent
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Abstract
An ESD protection circuit includes a pair of NPN lateral transistors electrically connected in series with the emitter of one of the transistors electrically connected to the collector of the other transistor. The bases of the two transistors are electrically connected together and are floating. The two transistors may be provided by two MOS transistors having N-type source and drains and P-type channel regions. The channels regions are connected together and are floating.
Claims10
An ESD protection circuit comprising:
- a pair of lateral NPN transistors each having an emitter, a collector and a base, the transistors are connected in series with the emitter of one of the transistors being connected to the collector of the other transistor;
- a terminal connected to the collector of the one transistor;
- a separate terminal connected to the emitter of the other transistor;
- and
- means electrically connecting the bases of the transistors so that they are floating.
2 more elements
A semiconductor device forming an ESD protection circuit comprising:
- a substrate of single crystalline silicon having a surface;
- a layer of an insulating material over the surface of the substrate;
- a thin layer of single crystalline silicon over the insulating layer;
- a pair of NPN lateral transistors in the silicon layer with each transistor having a pair of spaced N type conductivity regions and a P-type conductivity region between and contacting the N-type region;
- one of the N-type regions of one of the transistors being electrically connected to one of the N-type regions of the other transistor;
- and
- means electrically connecting the P-type regions of the two transistors.
4 more elements
Dependencies are inferred from the claim text.