Multi-function viewer/tester for miniature electric components

A machine for applying a multiplicity of electrical tests to a surface-mount, computer capacitor chip having spaced-apart electrically-conductive ends, comprising:

• a) a first moving carrier belt including a free span wherein one surface of said carrier belt includes means for temporarily holding the computer capacitor chip in fixed position on said span;
• b) a second moving tester belt including outer and inner belt surfaces, said tester belt comprising:
• i) a plurality of closely-spaced, paired electrically conductive pads arranged along said outer belt surface to contact the opposed electrically-conductive ends of each capacitor chip when said second tester belt is brought into tangential contact with the computer capacitor chip positioned on said first belt;
• ii) a plurality of paired electrical traces, one each extending from each said electrically-conductive pad;
• iii) electrical conductors located at least partially in between said outer and said inner belt surfaces of said tester belt to electrically connect said individual pairs of said traces with individual wires exposed on said inner surface of said second belt;
• and,
• c) means for electrically interconnecting said exposed wires on said inner surface of said second belt with electrical test facilities.

A machine for applying a multiplicity of visual and electrical tests to a plurality of surface-mount computer capacitor chips, each chip defined by a top surface, bottom surface, spaced-apart side surfaces, and spaced-apart, electrically-conductive, opposed end surfaces, comprising:

• a) a loader for assembling an inventory of chips and feeding the chips outwardly in controlled manner and in a timed sequence;
• b) a first moving endless metal carrier belt arranged in racetrack pattern and including an upper surface, on which to receive the chips from said loader, a lower surface, and a free span wherein said first belt includes an area of perforations there through for temporarily holding a chip in fixed position by its bottom surface on said upper belt surface by vacuum applied from said lower belt surface thereby exposing the upper surface and sides of the chip for inspection;
• c) a chip, upper-surface viewing device for bringing the upper and side exposed surfaces of the moving chips into focus at an area for inspecting said upper and side exposed chip surfaces for visual defects including a lamp to illuminate the chip, and an imaging device for inspecting the illuminated portion of the chip;
• d) a second moving endless belt in racetrack pattern, said second belt having a partially perforated outer surface and a vacuum pulled through said perforations below said outer surface along a portion of said belt, said second belt located outside of said vacuum area of said first belt, for receipt of and holding the chips by their top surfaces thereof in similar spaced-apart arrangement thereby exposing the chip's uninspected bottom and conductive end surfaces for inspection;
• e) a chip, lower-surface viewing device for bringing the lower and exposed end surfaces of the chip into focus at an area for inspecting the chips for visual defects;
• f) means for adjusting the location and spacing of the chips on said second belt;
• g) a fourth moving endless belt in racetrack pattern, said fourth belt having a partially perforated outer surface and a vacuum pulled through said perforations below said outer surface along a portion of said belt, said fourth belt located outside of said vacuum area of said second belt, for receipt of and holding the chips by their bottom surface, said fourth belt including a free span where the chips may be moved along by said fourth belt with their electrically-conductive ends arranged sideways to the direction of movement of said fourth belt;
• h) a fifth moving endless tester belt in racetrack pattern, said fifth belt defined by outer and inner belt surfaces, and further comprising:
• i) a plurality of closely-spaced, paired electrically conductive pads located along said fifth belt outer surface and arranged to contact the opposed electrically-conductive ends of each chip when said tester belt is brought into tangential contact with the chip positioned on said fourth belt;
• ii) a plurality of paired electrical traces, one each extending outward along the surface of said fifth belt from each said electrically-conductive pad;
• iii) electrical conductors located at least partially between said outer and said inner belt surfaces of said tester belt to electrically connect said individual pairs of said traces with individual wires exposed on said inner surface of said fifth belt;
• and,
• i) means for electrically interconnecting said exposed wires on said inner surface of said fifth belt with electrical test facilities.