US 5,969,544 AGranted

Clock driver circuit and semiconductor integrated circuit device incorporating the clock driver circuit

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsTakenobu Iwao, Nobuyuki Ikeda, Miho Yokota

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Abstract

A plurality of macro cell layout regions 9 in cell regions 2 on a semiconductor substrate 1 are divided into three portions in a second direction. Each of the divided portions is provided with basic circuits 14a through 14c. In each basic circuit, a first common line 16 is connected to an output node of a clock input driver 11 via a clock output line 17. A plurality of predrivers 15(1) through 15(n) have their input nodes IN connected to the first common line 16 and have their output nodes OUT connected to a second common line 18. A plurality of main drivers 19(1) through 19mhave their input nodes IN connected to the second common line 18 and have their output nodes OUT connected to a third common line 20. The third common line is connected to a plurality of clock signal supply lines 21(1) through 21(s) commonly provided to the basic circuits 14a through 14c. The clock signal supply lines 21(1) through 21(s) are connected to clock input nodes of internal circuits 22 each requiring a clock signal.

Claims14

Dependent claims

A clock driver circuit comprising:

a plurality of internal circuits formed on a principal plane of a semiconductor substrate and each requiring a clock signal;
a plurality of clock signal supply lines formed on said principal plane of said semiconductor substrate and connected electrically to clock input nodes of predetermined internal circuits among said plurality of internal circuits;
and
a plurality of basic circuits for each amplifying a received clock signal and supplying the clock signals to said plurality of clock signal supply lines;
each of said plurality of basic circuits comprising:
a first common line formed on said principal plane of said semiconductor substrate for receiving the clock signals;
a plurality of predrivers formed on said principal plane of said semiconductor substrate, input nodes of said plurality of predrivers being connected electrically to said first common line;
a second common line formed on said principal plane of said semiconductor substrate and connected electrically to output nodes of said plurality of predrivers;
a plurality of main drivers formed on said principal plane of said semiconductor substrate, input nodes of said plurality of main drivers being connected electrically to said second common line;
and
a third common line formed on said principal plane of said semiconductor substrate and connected electrically to output nodes of said plurality of main drivers and to said plurality of clock signal supply lines.

8 more elements

A semiconductor integrated circuit device comprising:

a plurality of internal circuits formed on a principal plane of a semiconductor substrate and each requiring a clock signal;
a plurality of clock signal supply lines formed linearly in a second direction and in parallel with one another on said principal plane of said semiconductor substrate, said plurality of clock signal supply lines being connected electrically to clock input nodes of predetermined internal circuits among said plurality of internal circuits;
and
a plurality of basic circuits formed in said second direction on said principal plane of said semiconductor substrate, said plurality of basic circuits each amplifying a received clock signal and supplying the clock signals to said plurality of clock signal supply lines;
each of said plurality of basic circuits comprising:
a first common line formed linearly in a first direction perpendicularly intersecting said second direction on said principal plane of said semiconductor substrate, said first common line receiving the clock signal;
a plurality of predrivers formed in said first direction and arranged predetermined distances apart on said principal plane of said semiconductor substrate, input nodes of said plurality of predrivers being connected electrically to said first common line;
a second common line formed linearly in said first direction on said principal plane of said semiconductor substrate and connected electrically to output nodes of said plurality of predrivers;
a plurality of main drivers formed in said first direction and arranged predetermined distances apart on said principal plane of said semiconductor substrate, input nodes of said plurality of main drivers being connected electrically to said second common line;
and
a third common line formed linearly in said first direction on said principal plane of said semiconductor substrate and connected electrically to output nodes of said plurality of main drivers and to said plurality of clock signal supply lines.

8 more elements

A semiconductor integrated circuit device comprising:

a semiconductor substrate having a plurality of macro cell layout regions arranged in a first direction on a principal plane of the substrate;
and
a plurality of electrode pairs arranged in a second direction perpendicularly intersecting said first direction in each of said plurality of macro cell layout regions of said semiconductor substrate;
wherein each of said plurality of macro cell layout regions includes a plurality of N-type diffusion areas each oriented in said second direction and a plurality of P-type diffusion areas each oriented in said second direction, said plurality of N-type diffusion areas and said plurality of P-type diffusion areas being formed collectively in said first direction;
wherein each of said plurality of electrode pairs is made up of a first and a second electrode, said first electrode being formed together with an interposing insulation film between a contiguous two of said plurality of N-type diffusion areas provided in each of said plurality of macro cell layout regions, said second electrode being formed together with an interposing insulation film between a contiguous two of said plurality of P-type diffusion areas which are arranged along with said first electrode in said first direction and which are provided in the macro cell layout region in question;
wherein each of said plurality of electrode pairs and the N- and P-type diffusion areas located on both sides of the electrode pair in question constitute a basic cell;
wherein a first macro cell which is made up of a predetermined number of contiguous basic cells and which acts as a logic circuit is provided to each of said plurality of macro cell layout regions on said semiconductor substrate;
wherein a second macro cell which is made up of a predetermined number of contiguous basic cells and which acts as an internal circuit requiring a clock signal is provided to each of at least two of said plurality of macro cell layout regions;
wherein each of said plurality of macro cell layout regions having said second macro cell has a plurality of clock signal supply lines arranged linearly in said second direction and connected electrically to a clock input node of an internal circuit acting as said second macro cell provided to the corresponding macro cell layout region;
wherein said plurality of macro cell layout regions on said semiconductor substrate are divided into a plurality of portions in said second direction, each of the divided portions being provided with a basic circuit;
and
wherein each of the basic circuits in the corresponding divided portion comprises:
a plurality of predrivers which are composed of a predetermined number of contiguous basic cells and which are linearly arranged, said plurality of predrivers being provided to each of at least two of said plurality of macro cell layout regions on said semiconductor substrate;
a plurality of main drivers which are composed of a predetermined number of contiguous basic cells, which are each provided with said plurality of predrivers and which are linearly arranged, said plurality of main drivers being provided to each of at least two macro cell layout regions other than those provided with said plurality of predrivers on said semiconductor substrate;
a first common line formed linearly in said first direction on said plurality of predrivers and said plurality of main drivers provided to the divided portion in question, said first common line being electrically connected to input nodes of said plurality of predrivers provided to the divided portion in question;
a second common line formed linearly in said first direction on said plurality of predrivers and said plurality of main drivers provided to the corresponding divided portion, said second common line being electrically connected to output nodes of said plurality of predrivers in the corresponding divided portion as well as to input nodes of said plurality of main drivers in the corresponding divided portion;
and
a third common line formed linearly in said first direction on said plurality of predrivers and said plurality of main drivers provided to the corresponding divided portion, said third common line being electrically connected to output nodes of said plurality of main drivers provided to the corresponding divided portion, said third common line being further connected electrically to said plurality of clock signal supply lines.

15 more elements

Dependencies are inferred from the claim text.