Semiconductor device comprising a plurality of interconnection patterns

A semiconductor integrated circuit formed on a semiconductor substrate, comprising:

• a plurality of semiconductor element groups provided on a surface of said semiconductor substrate, each performing a prescribed operation;
• a first interconnection pattern provided above said plurality of semiconductor element groups, used as a local line for connecting semiconductor elements in each of said semiconductor element groups;
• a second interconnection pattern provided above said first interconnection pattern;
• a third interconnection pattern provided above said second interconnection pattern;
• and
• a memory array region including a plurality of memory cells arranged in rows and columns on a surface of said semiconductor substrate, and a plurality of bit line pairs corresponding to said columns of the memory cells respectively,
• said first interconnection pattern being used as said bit line pairs, and thinner than said second interconnection pattern,
• said second interconnection pattern being thinner than said third interconnection pattern, wherein
• said second interconnection pattern is used as a lower layer signal line for signal input/output between each of said semiconductor element groups and a portion in the substrate other than the semiconductor element group;
• said third interconnection pattern is used as an upper layer power supply line for applying a power supply potential to each of said semiconductor element groups;
• the lower layer signal line and the upper layer power supply line extend parallel to each other;
• the local line extends orthogonal to the lower layer signal line and the upper layer power supply line;
• said second interconnection pattern is further used as a contact electrode for connecting said upper layer power supply line with each of said semiconductor element groups;
• and with no intervening conductive pattern between the lower layer signal line and third interconnection pattern.