Process for forming a morphological edge structure to seal integrated electronic devices, and corresponding device

An electronic device comprising:

• a semiconductor substrate having a major surface;
• an electronic circuit integrated in the major surface of the semiconductor substrate;
• and
• a device edge morphological structure for protecting and sealing peripherally the electronic circuit, said device edge morphological structure comprising
• an intermediate process structure comprising a first layer of conducting material, and
• a dielectric multilayer over the intermediate process structure and comprising a layer of amorphous planarizing material having an end portion delimited by joined together upper and lower layers of dielectric material, said dielectric multilayer having a peripheral termination on said first layer of conducting material in the device edge morphological structure placed at a higher level than a level of the major surface compared with adjacent zones of the intermediate process structure at least internally towards the electronic circuit and in so far as to the device edge morphological structure.