US 5,969,395 AGranted

Integrated circuit memory devices with high and low dopant concentration regions of different diffusivities

AssigneeSamsung Electronics Co., Ltd.

InventorKyu-pil Lee

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Abstract

An integrated circuit memory device includes a substrate divided into a cell array region, a core region, and a peripheral circuit region. A plurality of memory cells in the memory cell region each comprise a memory cell transistor having first spaced apart source/drain regions of the substrate with a predetermined conductivity. A sensing circuit in the core region of the substrate includes a sensing transistor having second spaced apart source/drain regions of the substrate. Each of the second source/drain regions includes high and low concentration regions of the predetermined conductivity wherein the high and low concentration regions are doped with a common dopant. A peripheral circuit in the peripheral region of the substrate includes a peripheral transistor having third spaced apart source/drain regions wherein each of the third source/drain regions has high and low concentration regions thereof. The high concentration region of the third source/drain regions has a first dopant and the low concentration region of the third source/drain region has a second dopant. Related methods are also discussed.

Claims19

Dependent claims

An integrated circuit memory device comprising:

a substrate including a cell array region, a core region, and a peripheral circuit region;
a plurality of memory cells in said cell array region of said substrate wherein each of said memory cells comprises a memory cell transistor including first spaced apart source/drain regions of said substrate, wherein said first source/drain regions have a predetermined conductivity;
a sensing circuit in said core region of said substrate wherein said sensing circuit comprises a sensing transistor including second spaced apart source/drain regions of said substrate wherein each of said second source/drain regions comprises high and low concentration regions of said predetermined conductivity and wherein said high and low concentration regions comprise a common dopant;
and
a peripheral circuit in said peripheral region of said substrate wherein said peripheral circuit comprises a peripheral transistor including third spaced apart source/drain regions of said substrate wherein each of said third source/drain regions comprises high and low concentration regions of said predetermined conductivity and wherein said high concentration region of said third source/drain regions comprises a first dopant and said low concentration region of said third source/drain regions comprises a second dopant different than the first dopant;
wherein said second source/drain regions of said sensing transistor are free of said second dopant.

3 more elements

Dependencies are inferred from the claim text.