Flash memory having separate data programming and erasing terminals

A flash memory for the programmable storage of data, comprising:

• a protruding plateau on a surface of a silicon substrate, wherein the protruding plateau has a base, a top surface, and first and second sidewalls;
• a drain region, having first and second sidewalls and being disposed on the top surface of the protruding plateau;
• a program source region in the substrate, disposed adjacent to a first side of the base of the protruding plateau;
• an erase source region in the substrate, disposed adjacent to the base of the protruding plateau on a second side of the base opposite the first side of the base;
• a first gate oxide layer on the first sidewall of the protruding plateau, wherein the first gate oxide layer has a sidewall and covers only a portion of the first sidewall of the drain region;
• a second gate oxide layer on the second sidewall of the protruding plateau, wherein the second gate oxide layer has a sidewall and covers only a portion of the second sidewall of the drain region;
• a first tunnel oxide layer over the program source region, wherein the first tunnel oxide layer is thinner than the first gate oxide layer and further is thinner than the second gate oxide layer;
• a second tunnel oxide layer over the erase source region, wherein the second tunnel oxide layer is thinner than the first gate oxide layer and further is thinner than the second gate oxide layer;
• a third tunnel oxide layer over the drain region, wherein the third tunnel oxide layer is thinner than the first gate oxide layer and further is thinner than the second gate oxide layer;
• a program floating gate terminal layer on the sidewall of the first gate oxide layer and the first tunnel oxide layer;
• an erase floating gate terminal layer on the sidewall of the second gate oxide layer and the second tunnel oxide layer;
• a dielectric layer, having first and second sidewalls and being disposed over the substrate;
• a program controlling gate terminal layer on the first sidewall of the dielectric layer, for accepting a first voltage input to control programming of data to be stored on the flash memory;
• and
• an erase controlling gate terminal layer on the second sidewall of the dielectric layer, for accepting a second voltage input to control erasing of data stored on the flash memory.